IS43DR16640A-25DBLI ISSI, Integrated Silicon Solution Inc, IS43DR16640A-25DBLI Datasheet - Page 22
![no-image](/images/manufacturer_photos/0/3/347/issi__integrated_silicon_solution_inc_sml.jpg)
IS43DR16640A-25DBLI
Manufacturer Part Number
IS43DR16640A-25DBLI
Description
Manufacturer
ISSI, Integrated Silicon Solution Inc
Type
DDR2 SDRAMr
Datasheet
1.IS43DR16640A-25DBLI.pdf
(28 pages)
Specifications of IS43DR16640A-25DBLI
Organization
64Mx16
Density
1Gb
Address Bus
16b
Access Time (max)
400ps
Maximum Clock Rate
800MHz
Operating Supply Voltage (typ)
1.8V
Package Type
FBGA
Operating Temp Range
-40C to 85C
Operating Supply Voltage (max)
1.9V
Operating Supply Voltage (min)
1.7V
Pin Count
84
Mounting
Surface Mount
Operating Temperature Classification
Industrial
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IS43DR16640A-25DBLI
Manufacturer:
ISSI
Quantity:
126
IS43/46DR81280A, IS43/46DR16640A
AC Characteristics
(AC Operating Conditions Unless Otherwise Noted)
Integrated Silicon Solution, Inc. – www.issi.com –
Rev. 00D, 8/17/2010
Input Setup Time (fast
slew rate)
Input Hold Time (fast slew
rate)
Input Pulse Width
Write DQS High Level
Width
Write DQS Low Level
Width
CLK to First Rising Edge of
DQS‐In
Data‐In Setup Time to
DQS‐In (DQ, DM)
Data‐In Hold Time to
DQS‐In (DQ, DM)
DQS falling edge from CLK
rising Setup Time
DQS falling edge from CLK
rising Hold Time
DQ & DM Pulse Width
Read DQS Preamble Time
Read DQS Postamble
Time
Write DQS Preamble
Setup Time
Write DQS Preamble Hold
Time
Write DQS Preamble Time
Write DQS Postamble
Time
Internal Read to
Precharge Command
Delay
Internal Write to Read
Command Delay
Data‐Out to High
Impedance from CK/CK#
DQS/DQS# Low
Impedance from CK/CK#
Parameter
tLZ(DQS)
tWPREH
tWPRES
Symbol
tWPRE
tDQSH
tWPST
tDQSL
tDQSS
tDIPW
tRPRE
tRPST
tWTR
tIPW
tDSH
tDSS
tRTP
tDH
tDS
tHZ
tIH
tIS
0.35
0.35
0.35
0.25
0.35
DDR2‐533C DDR2‐667D DDR2‐800E
Min Max Min Max Min Max Min
250
375
100
225
0.6
0.2
0.2
0.9
0.4
0.4
7.5
7.5
0
‐37C
1.1
0.6
0.6
Min = tAC(min), Max = tAC(max)
Min = ‐0.25tCK, Max = +0.25tCK
0.35
0.35
0.35
0.25
0.35
200
275
100
175
Min = n/a, Max = tAC(max)
0.6
0.2
0.2
0.9
0.4
0.4
7.5
7.5
0
‐3D
1.1
0.6
0.6
0.35
0.35
0.35
0.25
0.35
175
250
125
0.6
0.2
0.2
0.9
0.4
0.4
7.5
7.5
50
0
‐25E
1.1
0.6
0.6
0.35
0.35
0.35
0.25
0.35
175
250
125
0.6
0.2
0.2
0.9
0.4
0.4
7.5
7.5
DDR2‐800D
50
0
‐25D
Max
1.1
0.6
0.6
Units
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
ps
ps
ps
ps
ns
ns
ns
ns
16,17,
16,17,
Notes
15,17
15,17
18
18
10
13
7
7
22