IS43DR16640A-25DBLI ISSI, Integrated Silicon Solution Inc, IS43DR16640A-25DBLI Datasheet - Page 23

• Manufacturer Part Number: IS43DR16640A-25DBLI
• Manufacturer: ISSI, Integrated Silicon Solution Inc
• Type: DDR2 SDRAMr

Specifications of IS43DR16640A-25DBLI

• Organization: 64Mx16
• Density: 1Gb
• Address Bus: 16b
• Access Time (max): 400ps
• Maximum Clock Rate: 800MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: FBGA
• Operating Temp Range: -40C to 85C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Pin Count: 84
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Compliant

IS43/46DR81280A, IS43/46DR16640A
AC Characteristics
(AC Operating Conditions Unless Otherwise Noted)
Notes:
1.
2.
Integrated Silicon Solution, Inc. – www.issi.com –
Rev. 00D, 8/17/2010
DQ to Low Impedance from
CK/CK#
Mode Register Set Delay
OCD Drive Mode Output
Delay
ODT Drive Mode Output
Delay
Exit Self refresh to Non‐Read
Command
Exit Self refresh to Read
Command
Exit Precharge Power Down
to any Non‐Read Command
Exit Active Power Down to
Read Command
Exit Active Power Down to
Read Command (slow exit,
low power)
Minimum time clocks
remains ON after CKE
asynchronously drops LOW
CKE minimum high and low
pulse width
Average Periodic Refresh
Interval (‐40°C ≤ T
Average Periodic Refresh
Interval (+85°C < T
Average Periodic Refresh
Interval
Period Jitter
Half Period Jitter
Cycle to Cycle Jitter
Cumulative error, 2 cycles
Cumulative error, 3 cycles
Cumulative error, 4 cycles
Cumulative error, 5 cycles
Cumulative error, 6‐10 cycles
Cumulative error, 11‐50
cycles
Input slew rate is 1 V/ns and AC timings are guaranteed for linear signal transitions.
The CK/CK# input reference level (for timing reference to CK/CK#) is the point at which CK and CK# cross the DQS/DQS# input reference level is the cross point
when in differential strobe mode; the input reference level for signals other than CK/CK#, or DQS/DQS# is VREF.
(+95°C < T
Parameter
C
C
C
≤ +85° C)
≤ +105° C)
≤ +95° C)
tERR(2PER)
tERR(3PER)
tERR(4PER)
tERR(5PER)
(11‐50PER)
(6‐10PER)
tLZ(DQ)
Symbol
tAXRDS
tJITDTY
tDELAY
tJITPER
tXSNR
tXARD
tMOD
tXSRD
tJITCC
tMRD
tREFI
tREFI
tREFI
tCKE
tERR
tERR
tOIT
tXP
6‐AL
‐125
‐125
‐250
‐175
‐225
‐250
‐250
‐350
‐450
Min
200
DDR2‐533C
2
0
0
2
2
3
‐37C
Max
125
125
250
175
225
250
250
350
450
7.8
3.9
3.9
12
12
Min = 2 x tAC(min), Max = tAC(max)
7‐AL
Min = t
‐125
‐125
‐250
‐175
‐225
‐250
‐250
‐350
‐450
Min
Min = t
200
DDR2‐667D
2
0
0
2
2
3
‐3D
IS
RFC
Max
+t
125
125
250
175
225
250
250
350
450
7.8
3.9
3.9
12
12
+ 10, Max = n/a
CK
+t
IH
, Max = n/a
8‐AL
‐100
‐100
‐200
‐150
‐175
‐200
‐200
‐300
‐450
Min
200
DDR2‐800E
2
0
0
2
2
3
‐25E
Max
100
100
200
150
175
200
200
300
450
7.8
3.9
3.9
12
12
8‐AL
‐100
‐100
‐200
‐150
‐175
‐200
‐200
‐300
‐450
Min
200
DDR2‐800D
2
0
0
2
2
3
‐25D
Max
100
100
200
150
175
200
200
300
450
7.8
3.9
3.9
12
12
Units
tCK
ns
ns
ns
ns
t
t
t
t
ns
t
μs
μs
μs
ps
ps
ps
ps
ps
ps
ps
ps
ps
CK
CK
CK
CK
CK
Notes
18, 23
18, 23
18, 23
19
14
22
22
22
22
22
22
22
22
22
7
9
23