MT46H32M16LFCK-10 Micron Technology Inc, MT46H32M16LFCK-10 Datasheet - Page 62

• Manufacturer Part Number: MT46H32M16LFCK-10
• Manufacturer: Micron Technology Inc
• Type: DDR SDRAMr

Specifications of MT46H32M16LFCK-10

• Organization: 32Mx16
• Density: 512Mb
• Address Bus: 15b
• Access Time (max): 7ns
• Maximum Clock Rate: 104MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: VFBGA
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 90mA
• Pin Count: 60
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

Notes
PDF: 09005aef818ff7c5/Source: 09005aef81a6c5f3
MT46H32M16LF_2..fm - Rev. F 09/05 EN
Notes: 1. All voltages referenced to V
10. I
11. Enables on-chip refresh and address counters.
12. I
13. This parameter is sampled. V
14. Fast Command/Address input slew rate ≥ 1V/ns. Slow Command/Address input slew
15.
2. All parameters assume proper device initialization.
3. Tests for AC timing, I
4. Outputs measured with equivalent load:
5. Timing and I
6. All AC timings assume an input slew rate of 1V/ns.
7. CAS latency definition: with CL = 2 the first data element is valid at (
8. V
9. The value of V
at nominal supply voltage levels, but the related specifications and device operation
are guaranteed for the full voltage range specified.
but input timing is still referenced to V
The output timing reference voltage level is V
the clock at which the READ command was registered, for CL = 3 the first data ele-
ment is valid at (2 x
registered.
level on CK#.
track variations in the DC level of the same.
with minimum cycle time at CL = 2 for -10 and CL = 3 for -75 with the outputs open.
after test condition is met.
25ºC, V
pins, reflecting the fact that they are matched in loading.
rate ≥ 0.5V/ns. If the slew rate is less than 0.5V/ns, timing must be de-rated:
additional 50ps per each 100mV/ns reduction in slew rate from the 0.5V/ns.
0ps added, that is, it remains constant. If the slew rate exceeds 4.5V/ns, functionality
is uncertain.
t
tions. These parameters are not referenced to a specific voltage level, but specify
when the device output is no longer driving (HZ) or begins driving (LZ).
HZ and
DD
DD
I/O
I/O
ID
Half-drive strength
Full-drive strength
is the magnitude of the difference between the input level on CK and the input
specifications are tested after the device is properly initialized, and is averaged
is dependent on output loading and cycle rates. Specified values are obtained
OUT
50
t
50
LZ transitions occur in the same access time windows as valid data transi-
(
DC
DD
) = V
IX
tests may use a V
is expected to equal V
20 pF
10 pF
DD
t
CK +
DD
Q/2, V
, and electrical AC and DC characteristics may be conducted
t
62
SS
AC) after the first clock at which the READ command was
OUT
.
DD
(peak-to-peak) = 0.2V. DM input is grouped with I/O
= +1.8V ±0.1V, V
IL
-to-V
Micron Technology, Inc., reserves the right to change products or specifications without notice.
512Mb: x16, x32 Mobile DDR SDRAM
IH
DD
DD
swing of up to 1.5V in the test environment,
Q/2 (or to the crossing point for CK/CK#).
Q/2 of the transmitting device and must
DD
Q/2.
DD
Q = +1.8V ±0.1V, f = 100 MHz, T
©2005 Micron Technology, Inc. All rights reserved.
t
CK +
t
t
AC) after
IS has an
Advance
Notes
t
IH has
A
=