IS42S16100F-7BLI ISSI, Integrated Silicon Solution Inc, IS42S16100F-7BLI Datasheet - Page 38

• Manufacturer Part Number: IS42S16100F-7BLI
• Manufacturer: ISSI, Integrated Silicon Solution Inc

Specifications of IS42S16100F-7BLI

• Lead Free Status / Rohs Status: Compliant

IS42/45S16100F, IS42VS16100F
Read Cycle (Full Page) Interruption Using
the Burst Stop Command
The SDRAM can output data continuously from the burst
start address (a) to location a+255 during a read cycle
in which the burst length is set to full page. The SDRAM
repeats the operation starting at the 256th cycle with the
data output returning to location (a) and continuing with a+1,
a+2, a+3, etc. A burst stop command must be executed
to terminate this cycle. A precharge command must be
executed within the ACT to PRe command period (t
max.) following the burst stop command.
38
CAS latency = 3, burstlength = 4
CAS latency = 2, burstlength = 4
COMMAND
COMMAND
CLK
CLK
DQ
DQ
READ (CA=A, BANK 0)
READ (CA=A, BANK 0)
READ A0
READ A0
D
OUT
A0 D
D
ras
OUT
OUT
A0
A0 D
After the period (t
stop following the execution of the burst stop command
has elapsed, the outputs go to the HIGH impedance
state. This period (t
CAS latency is two and three clock cycle when the CAS
latency is three.
D
OUT
OUT
Integrated Silicon Solution, Inc. — www.issi.com
CAS Latency
A1
A0
BURST STOP
BURST STOP
t
rbd
D
D
OUT
OUT
BST
BST
A2
A1
rbd
rbd
) required for burst data output to
t
RBD
D
D
) is two clock cycle when the
OUT
OUT
t
RBD
A3
A2
3
3
D
OUT
HI-Z
A3
HI-Z
2
2
06/03/2010
Rev. 00C