MT36JSZF1G72PZ-1G4D1 Micron Technology Inc, MT36JSZF1G72PZ-1G4D1 Datasheet - Page 4

• Manufacturer Part Number: MT36JSZF1G72PZ-1G4D1
• Description: MODULE DDR3 SDRAM 8GB 240RDIMM
• Manufacturer: Micron Technology Inc
• Series: -r

Specifications of MT36JSZF1G72PZ-1G4D1

• Main Category: DRAM Module
• Sub-category: DDR3 SDRAM
• Module Type: 240RDIMM
• Device Core Size: 72b
• Organization: 1Gx72
• Total Density: 8GByte
• Maximum Clock Rate: 1.333GHz
• Operating Supply Voltage (typ): 1.5V
• Operating Current: 3.006A
• Number Of Elements: 36
• Operating Supply Voltage (max): 1.575V
• Operating Supply Voltage (min): 1.425V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 240
• Mounting: Socket
• Memory Type: DDR3 SDRAM
• Memory Size: 8GB
• Speed: 1333MT/s
• Features: -
• Package / Case: 240-RDIMM
• Lead Free Status / Rohs Status: Compliant

Table 6: Pin Descriptions
PDF: 09005aef83992c00
jszf36c512_1gx72pz.pdf - Rev. C 4/10 EN
RAS#, CAS#,
DQS#[17:0]
DQS[17:0],
CK0, CK0#
ODT[1:0]
DQ[63:0]
Err_Out#
Symbol
CKE[1:0]
A[15:0]
BA[2:0]
RESET#
SA[2:0]
CB[7:0]
S#[1:0]
Par_In
WE#
SDA
SCL
(open drain)
(LVCMOS)
Output
Type
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O
I/O
I/O
I/O
Description
Address inputs: Provide the row address for ACTIVATE commands, and the column ad-
dress and auto precharge bit (A10) for READ/WRITE commands, to select one location out
of the memory array in the respective bank. A10 is sampled during a PRECHARGE com-
mand to determine whether the PRECHARGE applies to one bank (A10 LOW, bank
selected by BA[2:0]) or all banks (A10 HIGH). If only one bank is to be precharged, the
bank is selected by BA. A12 is also used for BC4/BL8 identification as “BL on-the-fly” dur-
ing CAS commands. The address inputs also provide the op-code during the mode regis-
ter command set. A[13:0] address the 1Gb DDR3 devices. A[14:0] address the 2Gb DDR3
devices. A15 is needed to calculate parity on the command/address bus.
Bank address inputs: BA[2:0] define the device bank to which an ACTIVATE, READ,
WRITE, or PRECHARGE command is being applied. BA[2:0] define which mode register
(MR0, MR1, MR2, and MR3) is loaded during the LOAD MODE command. BA[2:0] are used
as part of the parity calculation.
Clock: CK and CK# are differential clock inputs. All control, command, and address input
signals are sampled on the crossing of the positive edge of CK and the negative edge of
CK#. Output data (DQ, DQS, and DQS#) is referenced to the crossings of CK and CK#.
Clock enable: CKE enables (registered HIGH) and disables (registered LOW) internal cir-
cuitry and clocks on the DRAM.
On-die termination: ODT enables (registered HIGH) and disables (registered LOW) termi-
nation resistance internal to the DDR3 SDRAM. When enabled in normal operation, ODT
is only applied to the following pins: DQ, DQS, DQS#, and DM. The ODT input will be
ignored if disabled via the LOAD MODE command.
Parity input: Parity bit for the address, RAS#, CAS#, and WE#.
Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being en-
tered.
Reset: RESET# is an active LOW CMOS input referenced to V
is a CMOS input defined as a rail-to-rail signal with DC HIGH ≥ 0.8 × V
0.2 × V
Chip select: S# enables (registered LOW) and disables (registered HIGH) the command
decoder.
Serial address inputs: These pins are used to configure the temperature sensor/SPD EE-
PROM address range on the I
Serial clock for temperature sensor/SPD EEPROM: SCL is used to synchronize commu-
nication to and from the temperature sensor/SPD EEPROM.
Check bits: Data used for ECC.
Data input/output: Bidirectional data bus.
Data strobe: DQS and DQS# are differential data strobes. Output with read data. Edge-
aligned with read data. Input with write data. Center-aligned with write data.
Serial data: SDA is a bidirectional pin used to transfer addresses and data into and out
of the temperature sensor/SPD EEPROM on the module on the I
Parity error output: Parity error found on the command and address bus.
DD
.
4GB, 8GB (x72, ECC, DR) 240-Pin DDR3 SDRAM RDIMM
4
2
C bus.
Micron Technology, Inc. reserves the right to change products or specifications without notice.
Pin Assignments and Descriptions
SS
. The RESET# input receiver
© 2009 Micron Technology, Inc. All rights reserved.
2
C bus.
DD
and DC LOW ≤