MT48H8M32LFB5-10:G Micron Technology Inc, MT48H8M32LFB5-10:G Datasheet - Page 12

• Manufacturer Part Number: MT48H8M32LFB5-10:G
• Manufacturer: Micron Technology Inc
• Type: Mobile SDRAMr

Specifications of MT48H8M32LFB5-10:G

• Organization: 8Mx32
• Density: 256Mb
• Address Bus: 14b
• Access Time (max): 17/8/7ns
• Maximum Clock Rate: 104MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: VFBGA
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 65mA
• Pin Count: 90
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

Commands
Operation, provides a quick reference of available
commands. This is followed by a written description of
Table 7:
CKE is HIGH for all commands shown except SELF REFRESH and DEEP POWER DOWN
NOTE:
COMMAND INHIBIT
commands from being executed by the SDRAM,
regardless of whether the CLK signal is enabled. The
SDRAM is effectively deselected and the DQ pins
tristate. Operations already in progress are not
affected.
pdf: 09005aef80d460f2, source: 09005aef80cd8d41
256Mb SDRAM x32_2.fm - Rev. D 9/04 EN
NAME (FUNCTION)
COMMAND INHIBIT (NOP)
NO OPERATION (NOP)
ACTIVE (Select bank and activate row)
READ (Select bank and column, and start READ burst)
WRITE (Select bank and column, and start WRITE burst)
BURST TERMINATE or DEEP POWER DOWN
(Enter deep power down mode)
PRECHARGE (Deactivate row in bank or banks)
AUTO REFRESH or SELF REFRESH
(Enter self refresh mode)
LOAD MODE REGISTER
Write Enable/Output Enable
Write Inhibit/Output High-Z
1. A0–A11 provide row address, and BA0, BA1 determine which bank is made active.
2. A0–A8 provide column address; A10 HIGH enables the auto precharge feature (non persistent), while A10 LOW disables
3. This command is BURST TERMINATE when CKE is high and DEEP POWER DOWN when CKE is low.
4. The purpose of the BURST TERMINATE command is to stop a data burst, thus the command could coincide with data on
5. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks precharged and BA0, BA1 are “Don’t
6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE.
8. A0–A11 define the op-code written to the Mode and Extended Mode register.
9. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay). DQM0 controls DQ0-
Table Table 7:, Truth Table – Commands and DQM
The COMMAND INHIBIT function prevents new
the auto precharge feature; BA0, BA1 determine which bank is being read from or written to.
the bus. However the DQs column reads a don’t care state to illustrate that the BURST TERMINATE command can occur
when there is no data present.
Care.”
DQ7; DQM1 controls DQ8-DQ15; DQM2 controls DQ16-DQ23; and DQM3 control DQ24-DQ31.
Truth Table – Commands and DQM Operation
CS# RAS# CAS# WE#
H
X
X
12
L
L
L
L
L
L
L
L
each command. Three additional Truth Tables appear
following the Operation section; these tables provide
current state/next state information.
NO Operation (NOP)
perform a NOP to an SDRAM which is selected (CS# is
LOW). This prevents unwanted commands from being
registered during idle or wait states. Operations
already in progress are not affected.
LOAD mode register
See mode register heading in the Register Definition
section. The LOAD MODE REGISTER and LOAD
X
H
H
H
H
X
X
The NO OPERATION (NOP) command is used to
The mode register is loaded via inputs A0, BA0, BA1.
L
L
L
L
Micron Technology, Inc., reserves the right to change products or specifications without notice.
H
H
H
H
X
X
X
L
L
L
L
X
H
H
H
H
X
X
L
L
L
L
DQM
L/H
L/H
H
X
X
X
X
X
X
X
L
8
8
MOBILE SDRAM
Bank/Row
©2003 Micron Technology, Inc. All rights reserved.
Bank/Col
Bank/Col
Op-Code
ADDR
Code
X
X
X
X
X
X
256Mb: x32
PRELIMINARY
High-Z
Active
Valid
DQS
X
X
X
X
X
X
X
X
NOTES
3, 4
6, 7
1
2
2
5
8
9
9