MT49H8M36FM-5 Micron Technology Inc, MT49H8M36FM-5 Datasheet - Page 23

• Manufacturer Part Number: MT49H8M36FM-5
• Manufacturer: Micron Technology Inc
• Type: RLDRAMr

Specifications of MT49H8M36FM-5

• Organization: 8Mx36
• Density: 288Mb
• Address Bus: 22b
• Maximum Clock Rate: 200MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: uBGA
• Operating Temp Range: 0C to 95C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 567mA
• Pin Count: 144
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Not Compliant

Input Slew Rate Derating
PDF: 09005aef80a41b59/Source: 09005aef809f284b
288Mb_RLDRAM_II_CIO_D2.fm - Rev N 5/08 EN
Note:
Table 10 on page 22 and Table 11 on page 23 define the address, command, and data
setup and hold derating values. These values are added to the default
t
the 2 V/ns the nominal setup and hold specifications are based upon.
To determine the setup and hold time needed for a given slew rate, add the
default specification to the “
specification to the "
derated data setup and hold values can be determined in a like manner using the “
V
derating values on Table 10 and Table 11 apply to all speed grades.
The setup times on Table 10 and Table 11 represent a rising signal. In this case, the time
from which the rising signal crosses V
must be maintained across all slew rates. The derated setup timing represents the point
at which the rising signal crosses V
is calculated by determining the time needed to maintain the given slew rate and the
delta between V
and Table 11 are also valid for falling signals (with respect to V
CK# cross point).
The hold times in Table 10 and Table 11 represent falling signals. In this case, the time
from the CK/CK# cross point to when the signal crosses V
be maintained across all slew rates. The derated hold timing represents the delta
between the CK/CK# cross point to when the falling signal crosses V
derated value is calculated by determining the time needed to maintain the given slew
rate and the delta between the CK/CK# cross point and V
Table 10 and Table 11 are also valid for rising signals (with respect to V
the CK and CK# cross point).
AH/
REF
The above descriptions also pertain to data setup and hold derating when CK/CK# are
replaced with DK/DK#.
t
to CK/CK# Crossing” and “
CH/
288Mb: x9, x18, x36 2.5V V
t
DH specifications when the slew rate of any of these input signals is less than
IH
(
AC
t
AH/
) MIN and the CK/CK# cross point. The setup values in Table 10
t
CH CK/CK# Crossing to V
t
AS/
23
t
DH to CK/CK# Crossing to V
t
CS V
REF
(
REF
IH
DC
Micron Technology, Inc., reserves the right to change products or specifications without notice.
(
Electrical Specifications – AC and DC
AC
) to the CK/CK# cross point. This derated value
to CK/CK# Crossing” and the
EXT
) MIN to the CK/CK# cross point is static and
, 1.8V V
REF
" derated values on Table 10. The
DD
IH
IH
, HSTL, CIO, RLDRAM II
(
(
REF
DC
DC
IL
©2003 Micron Technology, Inc. All rights reserved.
). The hold values in
) MIN is static and must
” values on Table 11. The
[
AC
] MAX and the CK/
REF
t
IL
AS/
t
(
AH/
[
DC
DC
t
CS/
). This
] MAX and
t
t
AS/
CH default
t
DS and
t
CS
t
DS