N25Q128A11B1240E NUMONYX, N25Q128A11B1240E Datasheet - Page 42

• Manufacturer Part Number: N25Q128A11B1240E
• Manufacturer: NUMONYX

Specifications of N25Q128A11B1240E

• Cell Type: NOR
• Density: 128Mb
• Access Time (max): 7ns
• Interface Type: Serial (SPI)
• Boot Type: Bottom
• Address Bus: 1b
• Operating Supply Voltage (typ): 1.8V
• Operating Temp Range: -40C to 85C
• Package Type: TBGA
• Program/erase Volt (typ): 1.7 to 2/8.5 to 9.5V
• Sync/async: Synchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 1.7V
• Operating Supply Voltage (max): 2V
• Word Size: 8b
• Number Of Words: 16M
• Supply Current: 20mA
• Mounting: Surface Mount
• Pin Count: 24
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Table 7.
6.4.1
6.4.2
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VECR<7>
VECR<6>
VECR<5>
VECR<4>
VECR<3>
VECR<2:0>
Bit
Volatile Enhanced Configuration Register
Quad Input Command VECR<7>
The Quad Input Command configuration bit can be used to make the memory start working
in QIO-SPI protocol directly after the Write Volatile Enhanced Configuration Register
(WRVECR) instruction. The default value of this bit is 1, corresponding to Extended SPI
protocol, If this bit is set to 0 the memory works in QIO-SPI protocol. If VECR bit 7 is set
back to 1 the memory start working again in Extended SPI protocol, unless the bit 6 is set to
0 (in this case the memory start working in DIO-SPI mode).
Please note that in case both QIO-SPI and DIO-SPI are enabled (both bit 7and bit 6 of the
VECR set to 0), the memory will work in QIO-SPI.
Dual Input Command VECR<6>
The Dual Input Command configuration bit can be used to make the memory start working
in DIO-SPI protocol directly after the Write Volatile Enhanced Configuration Register
(WVECR) instruction. The default value of this bit is 1, corresponding to Extended SPI
protocol, if this bit is set to 0 the memory works in DIO-SPI protocol (unless the Volatile
Enhanced Configuration Register bit 7 is also set to 0). If the Volatile Enhanced
Configuration Register bit 6 is set back to 1 the memory start working again in Extended SPI
protocol.
Please note that in case both QIO-SPI and DIO-SPI are enabled (both bit 7 and bit 6 of the
VECR are set to 0), the memory will work in QIO-SPI.
Quad Input Command
Dual Input Command
Reserved
Reset/Hold disable
Accelerator pin enable in
QIO-SPI protocol or in
QIFP/QIEFP
Output Driver Strength
Parameter
0
1
0
1
x
0
1
0
1
000
001
010
011
100
101
110
111
Value
Enabled
Disabled (default)
Enabled
Disabled (default)
Reserved
Disabled
Enabled (default)
Enabled
Disabled (default)
reserved
90
60
45
reserved
20
15
30 (default)
Description
Enable command on four input lines
Enable command on two input lines
Fixed value = 0b
Disable Pad Hold/Reset functionality
The bit must be considered in case of
QIFP, QIEFP, or QIO-SPI protocol. It is
“Don’t Care” otherwise.
Impedance at V
CC
Note
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