72T36115L4-4BBG Integrated Device Technology (Idt), 72T36115L4-4BBG Datasheet - Page 19

• Manufacturer Part Number: 72T36115L4-4BBG
• Description: FIFO Mem Async/Sync Dual Depth/Width Uni-Dir 128K x 36 240-Pin BGA
• Manufacturer: Integrated Device Technology (Idt)

Specifications of 72T36115L4-4BBG

• Package: 240BGA
• Configuration: Dual
• Bus Directional: Uni-Directional
• Density: 4.5 Mb
• Organization: 128Kx36
• Data Bus Width: 36 Bit
• Timing Type: Asynchronous|Synchronous
• Expansion Type: Depth|Width
• Typical Operating Supply Voltage: 2.5 V
• Operating Temperature: 0 to 70 °C

NOTES:
1. The programming method can only be selected at Master Reset.
2. Parallel reading of the offset registers is always permitted regardless of which programming method has been selected.
3. The programming sequence applies to both IDT Standard and FWFT modes.
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync™ ™ ™ ™ ™ 36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
LD
0
0
0
X
1
1
1
WEN
1
1
0
X
1
0
1
REN
Figure 3. Programmable Flag Offset Programming Sequence
0
1
1
1
X
0
1
SEN
1
1
0
1
X
X
X
WCLK
X
X
X
X
X
RCLK
19
X
X
X
X
X
SCLK
X
X
X
X
X
X
Serial shift into registers:
1 bit for each rising SCLK edge
Parallel read from registers:
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)
Starting with Empty Offset (LSB)
Ending with Full Offset (MSB)
Parallel write to registers:
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)
20 bits for the IDT72T3645
22 bits for the IDT72T3655
24 bits for the IDT72T3665
26 bits for the IDT72T3675
28 bits for the IDT72T3685
30 bits for the IDT72T3695
32 bits for the IDT72T36105
34 bits for the IDT72T36115
36 bits for the IDT72T36125
IDT72T3645, IDT72T3655
IDT72T3665, IDT72T3675
IDT72T3685, IDT72T3695
IDT72T36105, IDT72T36115
IDT72T36125
Read Memory
No Operation
Write Memory
No Operation
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
5907 drw06
FEBRUARY 4, 2009