72T36115L4-4BBG Integrated Device Technology (Idt), 72T36115L4-4BBG Datasheet - Page 55

• Manufacturer Part Number: 72T36115L4-4BBG
• Description: FIFO Mem Async/Sync Dual Depth/Width Uni-Dir 128K x 36 240-Pin BGA
• Manufacturer: Integrated Device Technology (Idt)

Specifications of 72T36115L4-4BBG

• Package: 240BGA
• Configuration: Dual
• Bus Directional: Uni-Directional
• Density: 4.5 Mb
• Organization: 128Kx36
• Data Bus Width: 36 Bit
• Timing Type: Asynchronous|Synchronous
• Expansion Type: Depth|Width
• Typical Operating Supply Voltage: 2.5 V
• Operating Temperature: 0 to 70 °C

OPTIONAL CONFIGURATIONS
WIDTH EXPANSION CONFIGURATION
signals of multiple devices. Status flags can be detected from any one device.
The exceptions are the EF and FF functions in IDT Standard mode and the IR
and OR functions in FWFT mode. Because of variations in skew between RCLK
and WCLK, it is possible for EF/FF deassertion and IR/OR assertion to vary
by one cycle between FIFOs. In IDT Standard mode, such problems can be
avoided by creating composite flags, that is, ANDing EF of every FIFO, and
Figure 36. Block Diagram of 1,024 x 72, 2,048 x 72, 4,096 x 72, 8,192 x 72, 16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72 and 262,144 x 72
NOTES:
1. Use an AND gate in IDT Standard mode, an OR gate in FWFT mode.
2. Do not connect any output control signals directly together.
3. FIFO #1 and FIFO #2 must be the same depth, but may be different word widths.
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync™ ™ ™ ™ ™ 36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
Word width may be increased simply by connecting together the control
GATE
(1)
FIRST WORD FALL THROUGH/
DATA IN
SERIAL INPUT (FWFT/SI)
SERIAL CLOCK (SCLK)
PARTIAL RESET (PRS)
MASTER RESET (MRS)
FULL FLAG/INPUT READY (FF/IR)
FULL FLAG/INPUT READY (FF/IR) #2
RETRANSMIT (RT)
m + n
PROGRAMMABLE (PAF)
WRITE CLOCK (WCLK)
WRITE ENABLE (WEN)
HALF-FULL FLAG (HF)
D
0
- D
LOAD (LD)
m
m
#1
72T36105
72T36115
72T36125
72T3645
72T3655
72T3665
72T3675
72T3685
72T3695
FIFO
IDT
#1
Width Expansion
D
m+1
m
- D
Q
55
n
0
n
- Qm
separately ANDing FF of every FIFO. In FWFT mode, composite flags can
be created by ORing OR of every FIFO, and separately ORing IR of every
FIFO.
72T3655/72T3665/72T3675/72T3685/72T3695/72T36105/72T36115/
72T36125 devices. D
Q
be attained by adding additional IDT72T3645/72T3655/72T3665/72T3675/
72T3685/72T3695/72T36105/72T36115/72T36125 devices.
0
-Q
Figure 36 demonstrates a width expansion using two IDT72T3645/
72T36105
72T36115
72T36125
72T3645
72T3655
72T3665
72T3675
72T3685
72T3695
35
FIFO
IDT
#2
from each device form a 72-bit wide output bus. Any word width can
READ CLOCK (RCLK)
READ CHIP SELECT (RCS)
n
READ ENABLE (REN)
OUTPUT ENABLE (OE)
EMPTY FLAG/OUTPUT READY (EF/OR) #2
EMPTY FLAG/OUTPUT READY (EF/OR) #1
PROGRAMMABLE (PAE)
Q
0
m+1
- D
35
- Q
from each device form a 72-bit wide input bus and
n
COMMERCIAL AND INDUSTRIAL
m + n
TEMPERATURE RANGES
DATA OUT
FEBRUARY 4, 2009
5907 drw41
GATE
(1)