LCMXO640C-3MN132C Lattice, LCMXO640C-3MN132C Datasheet - Page 57

• Manufacturer Part Number: LCMXO640C-3MN132C
• Description: CPLD MachXO Family 320 Macro Cells 1.8V/2.5V/3.3V 132-Pin CSBGA Tray
• Manufacturer: Lattice
• Series: MachXOr

Specifications of LCMXO640C-3MN132C

• Package: 132CSBGA
• Family Name: MachXO
• Number Of Macro Cells: 320
• Maximum Propagation Delay Time: 4.9 ns
• Number Of User I/os: 101
• Typical Operating Supply Voltage: 1.8|2.5|3.3 V
• Memory Type: SRAM
• Operating Temperature: 0 to 85 °C
• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 4.9ns
• Voltage Supply - Internal: 1.71 V ~ 3.465 V
• Number Of Logic Elements/blocks: -
• Number Of Macrocells: 320
• Number Of Gates: -
• Number Of I /o: 101
• Mounting Type: *
• Package / Case: *
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
LCMXO256 and LCMXO640 Logic Signal Connections: 100 csBGA (Cont.)
*NC for “E” devices.
**Primary clock inputs are single-ended.
Number
Ball
A14
H14
P10
C3
N9
G1
A4
B4
A3
B3
A2
A1
B2
B9
B5
P1
Function
GNDIO0
VCCIO0
VCCIO0
VCCIO0
VCCIO1
VCCIO1
VCCIO1
PT2D
PT2C
PT3A
PT2F
PT2E
PT2B
PT2A
GND
GND
Ball
LCMXO256
Bank
0
0
0
0
0
0
0
0
0
0
0
1
1
1
-
-
Function
Dual
Differen-
tial
C
C
C
T
T
T
T
4-13
Number
Ball
A14
H14
P10
G1
A4
B4
A3
B3
A2
C3
A1
B2
N9
B9
B5
P1
Function
GNDIO0
VCCIO0
VCCIO1
VCCIO1
VCCIO2
VCCIO3
VCCIO3
PT3B
PT3A
PT2E
PT2B
PT2C
PT2A
PT2F
GND
GND
Ball
MachXO Family Data Sheet
LCMXO640
Bank
0
0
0
0
0
0
0
0
0
1
1
2
3
3
-
-
Pinout Information
Function
Dual
Differen-
tial
C
C
C
T
T
T