STLC2415 STMicroelectronics, STLC2415 Datasheet
STLC2415
Specifications of STLC2415
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STLC2415 Summary of contents
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... Cameras Computer peripherals Other type of devices that require the wireless communication provided by Bluetooth 2 DESCRIPTION The STLC2415 from STMicroelectronics is a Blue- ® tooth baseband controller with integrated 4 Mbit flash memory. Together with a Bluetooth this product offers a compact and complete solu- tion for short-range wireless connectivity. It incor- ...
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... STLC2415 3 QUICK REFERENCE DATA 3.1 Absolute Maximum Ratings Operation of the device beyond these conditions is not guaranteed. Sustained exposure to these limits will adversely affect device reliability Table 2. Absolute Maximum Ratings Symbol V Supply voltage baseband core DD V Supply voltage flash DDF V Fast Program Voltage ...
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... High level output voltage oh Note the source/sink current under worst case conditions according to the drive capability. (See table 8, pad information for value of X). 3.4 Current Consumption Table 8. Typical Power Consumption of the STLC2415 (V 3.3V) STLC2415 State Standby (no low power mode) Standby (low power mode enabled) ...
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... STLC2415 Figure 2. Block Diagram and Electrical Schematic V DD 100nF V DDIO 100nF V DDIO 100nF 13 RADIO RF BUS I/F (*) 22pF LPOCLKP Y2 32KHz 22pF LPOCLKN VDDPLL V DD 100nF XIN (*) If a low-power clock is available, it can be connected to the LPOCLKP pin in stead of using a crystal (**) For device testing only (should not be connected in the application. ...
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... Pin Description and Asthe signment Table 9 shows the pin list of STLC2415. There are 91 functional pins of which 25 are used for device test- ing only (should not be connected in the application) and 24 supply pins. The column "PU/PD" shows the pads implementing an internal weak pull-up/down, to fix value if the pin is left open. This can not replace an external pull-up/down. The pads are grouped according to two different power supply values, as shown in column " ...
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... STLC2415 Table 9. Pin List Name Pin # Clock and test pins xin B18 System clock nreset A18 Reset nrp A17 External flash reset nwp H3 Flash Write Protect sys_clk_req C18 System clock request lpo_clk_p V9 Low power oscillator + / Slow clock input lpo_clk_n V10 Low power oscillator - ...
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... Gpio port 15 JTAG interface ntrst F18 JTAG pin tck D18 JTAG pin tms E16 JTAG pin tdi F16 JTAG pin Description STLC2415 DIR PU/PD VDD PAD O/t CMOS, 3.3V TTL V1 compatible, 2mA slew rate control I (2) CMOS, 3.3V TTL V1 compatible I/O ...
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... STLC2415 Table 9. Pin List (continued) Name Pin # tdo E18 JTAG pin (should be left open) PCM interface pcm_a A11 PCM data pcm_b C10 PCM data pcm_sync A12 PCM 8kHz sync pcm_clk C11 PCM clock Radio interface brclk L18 Transmit clock brxd M18 ...
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... G16 3.3V I/O's supply vss A3 Digital ground vss G1 Digital ground vss K1 Digital ground vss V1 Digital ground vss T9 Digital ground vssf L3 Digital ground Flash vssio C12 I/O's ground vssio C4 I/O's ground vssio T14 I/O's ground vssio D16 I/O's ground Description STLC2415 9/22 ...
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... STLC2415 Table 9. Pin List (continued) Name Pin # To be connected together on the PCB’s top layer ne D3 Flash chip enable csn0 E3 External chip select bank 0 Test Only (Do NOT connect) rdn/ng C3 External read csn1 D1 External chip select bank 1 csn2 E1 External chip select bank 2 ...
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... Extension of the ARM Bus to access the program in the integrated 4 MBit FLASH 5.3 Integrated Flash Memory – 4 Mbit size – 8 parameter blocks of 4 Kword (top configuration) – 7 main blocks of 32 Kword – 120 ns access time – See datasheet of standalone product M28R400CT for more detailed information. STLC2415 11/22 ...
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... STLC2415 Figure 4. Block Addresses 3FFFF 3F000 38FFF 38000 37FFF 30000 0FFFF 08000 07FFF 00000 5.3.1 Flash Signal Descriptions – Write Protect (nwp) Write protect is an input that gives an additional hardware protection for each block. When Write Protect is 0.4V the Lock-Down is enabled and the protection status of the flash blocks cannot be changed. ...
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... Vssf is the reference for all voltage measurements. – Address Inputs (Addr(1-18)/Addr(0-19)) * csn(0)) , Ouput Enable (ng/rdn) baseband controller flash memory signals / baseband controller signals ) * , Data Input/Output (Data(0-15)/Data(0-15 Write Enable (nw/wrn) are connected and controlled by the Bluetooth STLC2415 * , Chip Enable (ne/ ® 13/22 ...
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... STLC2415 (lpo_clk_p). – if the system clock (e.g. 13MHz) is provided at all times, the STLC2415 generates from the 13MHz ref- erence clock an internal 32kHz clock. This mode is not an optimized mode for power consumption. ...
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... HCI UART transport layer: – all HCI commands as described in the Bluetooth – ST specific HCI command (check STLC2415 Software Interface document for more information) – RXD, TXD, CTS, RTS on permanent external pins – 128-byte FIFOs, for transmit and for receive – ...
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... ARM7TDMI application when connected with the standard ARM7 devel- opment tools. 7.6 RF Interface The STLC2415 radio interface is compatible to BlueRF (unidirectional RxMode2 for data and unidirection- al serial interface for control). 7.7 PCM Voice Interface The PCM interface is a direct PCM interface to connect to a standard CODEC (e.g. STw5093 or STw5094) ...
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... Setup time, PCM_A/B input valid to PCM_CLK low SDC t Hold time, PCM_CLK low to PCM_A/B input invalid HCD t Delay time, PCM_CLK high to PCM_A/B output valid DCD 125 125 s Description Min Typ - 2048 8 200 200 200 100 100 100 STLC2415 B B D02TL558 D02TL559 Max Unit kHz kHz 150 ns 17/22 ...
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... HCI UART TRANSPORT LAYER The UART Transport Layer has been specified by the Bluetooth communication between a host controller (STLC2415) and a host (e.g. PC), via a RS232 interface. The objective of this HCI UART Transport Layer is to make it possible to use the Bluetooth serial interface between two UARTs on the same PCB. The HCI UART Transport Layer assumes that the UART communication is free from line errors ...
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... HCI USB TRANSPORT LAYER The USB Transport Layer has been specified by the Bluetooth munication between a host controller (STLC2415) and a host (e.g. PC), via a USB interface. The USB Transport Layer is completely implemented in SW. It accepts HCI messages from the HCI Layer, prepares it for transmission over a USB bus, and sends it to the USB Driver. It reassembles the HCI messages from USB data received from the USB Driver, and sends these messages to the HCI Layer. The Transport Lay- er does not interprete the contents (payload) of the HCI messages ...
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... STLC2415 Figure 10. LFBGA120 (Low Fne Ball Grid Array) Mechanical Data & Package Dimensions mm DIM. MIN. TYP. MAX. A 1. 0.25 0.30 0.35 D 9.90 10.00 10.10 D1 8.50 D2 6.50 E 9.90 10.00 10.10 E1 8.50 E2 6.50 eD 0.50 basic eE 0.50 basic FD 0. 120 balls SE 0.25 basic SD 0 ...
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... Editorial corrections. Clock support added in section 1. Section 2 corrected. Modified the figures 2 and 3. Modified the tables 5, 7 and 8. ‘To be connected’ added in table 9. Section 5.3.1 modified. Section 6.2 corrected. Section 6.5 modified. Section 7.3 updated and figure removed. Description of Changes STLC2415 21/22 ...
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... STLC2415 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice ...