PN5120A0HN/C1 NXP Semiconductors, PN5120A0HN/C1 Datasheet - Page 50
PN5120A0HN/C1
Manufacturer Part Number
PN5120A0HN/C1
Description
Transmission Module 40-Pin HVQFN EP T/R
Manufacturer
NXP Semiconductors
Datasheet
1.PN5120A0HN1C2118.pdf
(125 pages)
Specifications of PN5120A0HN/C1
Package
40HVQFN EP
Operating Temperature
-30 to 85 °C
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Product data sheet
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9.2.3.4 ModWidthReg
9.2.3.5 TxBitPhaseReg
Controls the modulation width settings.
Table 86.
Table 87.
Adjust the bitphase at 106 kbit during transmission.
Table 88.
Table 89.
Bit
7 to 0
Bit
7
6 to 0
Access
Rights
Access
Rights
RcvClkChange
Symbol
ModWidth
Symbol
RcvClkChange
TxBitPhase
ModWidthReg register (address 24h); reset value: 26h, 00100110b
Description of ModWidthReg bits
TxBitPhaseReg register (address 25h); reset value: 87h, 10000111b
Description of TxBitPhaseReg bits
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All information provided in this document is subject to legal disclaimers.
7
Rev. 3.6 — 10 March 2011
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Description
These bits define the width of the Miller modulation as initiator in Active
and Passive Communication mode as multiples of the carrier
frequency (ModWidth + 1/fc). The maximum value is half the bit
period.
Acting as a target in Passive Communication mode at 106 kbit or in
Card Operating mode for ISO/IEC 14443A/MIFARE these bits are
used to change the duty cycle of the subcarrier frequency.
The resulting number of carrier periods are calculated according to the
following formulas:
Description
Set to logic 1, the demodulator’s clock is derived by the external RF
field.
These bits are representing the number of carrier frequency clock
cycles, which are added to the waiting period before transmitting
data in all communication modes. TXBitPhase is used to adjust the
TX bit synchronization during passive NFCIP-1 communication mode
at 106 kbit and in ISO/IEC 14443A/MIFARE card mode.
LOW value: #clocksLOW = (ModWidth modulo 8) + 1.
HIGH value: #clocksHIGH = 16-#clocksLOW.
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111336
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ModWidth
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TxBitPhase
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Transmission module
© NXP B.V. 2011. All rights reserved.
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