C8051F336-GMR Silicon Laboratories Inc, C8051F336-GMR Datasheet - Page 125
C8051F336-GMR
Manufacturer Part Number
C8051F336-GMR
Description
Microcontrollers (MCU) 16KB 10ADC 10DAC 768Ram MCU Lead Free
Manufacturer
Silicon Laboratories Inc
Datasheet
1.C8051F336-GM.pdf
(226 pages)
Specifications of C8051F336-GMR
Processor Series
C8051F3x
Core
8051
Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
16 KB
Data Ram Size
768 B
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
17
Number Of Timers
4
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
QFN-20
3rd Party Development Tools
KSK-SL-TOOLSTICK, PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F336DK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
On-chip Dac
10 bit
Package
20QFN
Device Core
8051
Family Name
C8051F336
Maximum Speed
25 MHz
Ram Size
768 Byte
Operating Temperature
-40 to 85 °C
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F336-GMR
Manufacturer:
SILICON
Quantity:
100
Part Number:
C8051F336-GMR
Manufacturer:
SILICON LABS/芯科
Quantity:
20 000
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Registers XBR0 and XBR1 are used to assign the digital I/O resources to the physical I/O Port pins. Note
that when the SMBus is selected, the Crossbar assigns both pins associated with the SMBus (SDA and
SCL); when the UART is selected, the Crossbar assigns both pins associated with the UART (TX and RX).
UART0 pin assignments are fixed for bootloading purposes: UART TX0 is always assigned to P0.4; UART
RX0 is always assigned to P0.5. Standard Port I/Os appear contiguously after the prioritized functions
have been assigned.
Figure 20.5 shows an example of the resulting pin assignments of the device with UART0, SMBus, and
CEX0 enabled, the XTAL1 (P0.2) and XTAL2 (P0.3) pins skipped (P0SKIP = 0x0C). UART0 is the highest
priority and it will be assigned first. The UART can only appear on P0.4 and P0.5, so that is where it is
assigned. The next-highest enabled peripheral is the SMBus. P0.0 and P0.1 are free, so the SMBus takes
these two pins. The last peripheral enabled is the PCA’s CEX0 pin. P0.0, P0.1, P0.4 and P0.5 are already
occupied by higher-priority peripherals. Additionally, P0.2 and P0.3 are set to be skipped by the crossbar.
The CEX0 signal ends up getting routed to P0.6, as it is the next available pin. The other pins on the
device are available for use as general-purpose digital I/O or analog functions.
Important Note: The SPI can be operated in either 3-wire or 4-wire modes, pending the state of the
NSSMD1–NSSMD0 bits in register SPI0CN. According to the SPI mode, the NSS signal may or may not
be routed to a Port pin.
SF Signals
PIN I/O
TX0
RX0
SCK
MISO
MOSI
NSS
SDA
SCL
CP0
CP0A
SYSCLK
CEX0
CEX1
CEX2
ECI
T0
T1
SF Signals
1
VREF IDA
Port pin potentially available to peripheral
Special Function Signals are not assigned by the crossbar.
When these signals are enabled, the CrossBar must be
manually configured to skip their corresponding port pins.
0
0
1
0
Figure 20.5. Crossbar Priority Decoder Example
x1
2
1
P0SKIP[0:7]
x2
3
1
P0
4
0
5
0
CNVSTR
6
0
7
0
0
0
Rev.1.0
1
0
2
0
P1SKIP[0:7]
Notes:
1. NSS is only pinned out in 4-wire SPI Mode
2. Pins P2.1-P2.4 only on QFN24 Package
3. Pin 2.0 unavailable on crossbar in QFN20 Package
3
0
P1
4
0
5
0
C8051F336/7/8/9
6
0
7
0
0
0
P2SKIP[0:3]
1
0
2
P2
2
0
2
3
0
2
4
2
125
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