C8051F336-GMR Silicon Laboratories Inc, C8051F336-GMR Datasheet - Page 26
![Microcontrollers (MCU) 16KB 10ADC 10DAC 768Ram MCU Lead Free](/photos/16/2/160285/qfn-20_sml.jpg)
C8051F336-GMR
Manufacturer Part Number
C8051F336-GMR
Description
Microcontrollers (MCU) 16KB 10ADC 10DAC 768Ram MCU Lead Free
Manufacturer
Silicon Laboratories Inc
Datasheet
1.C8051F336-GM.pdf
(226 pages)
Specifications of C8051F336-GMR
Processor Series
C8051F3x
Core
8051
Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
16 KB
Data Ram Size
768 B
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
17
Number Of Timers
4
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
QFN-20
3rd Party Development Tools
KSK-SL-TOOLSTICK, PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F336DK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
On-chip Dac
10 bit
Package
20QFN
Device Core
8051
Family Name
C8051F336
Maximum Speed
25 MHz
Ram Size
768 Byte
Operating Temperature
-40 to 85 °C
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F336-GMR
Manufacturer:
SILICON
Quantity:
100
Part Number:
C8051F336-GMR
Manufacturer:
SILICON LABS/芯科
Quantity:
20 000
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- Download datasheet (2Mb)
C8051F336/7/8/9
26
Notes:
General
Solder Mask Design
Stencil Design
Card Assembly
Dimension
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This Land Pattern Design is based on the IPC-7351 guidelines.
3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder
4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used
5. The stencil thickness should be 0.125mm (5 mils).
6. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.
7. A 2x2 array of 1.10mm x 1.10mm openings on a 1.30mm pitch should be used for the center
8. A No-Clean, Type-3 solder paste is recommended.
9. The recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for
C1
C2
X1
E
mask and the metal pad is to be 60μm minimum, all the way around the pad.
to assure good solder paste release.
pad.
Small Body Components.
Figure 5.2. QFN-24 Recommended PCB Land Pattern
Table 5.2. QFN-24 PCB Land Pattern Dimesions
3.90
3.90
0.20
Min
0.50 BSC
0.30
Max
4.00
4.00
Rev.1.0
Dimension
X2
Y1
Y2
2.70
0.65
2.70
Min
Max
2.80
0.75
2.80
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