EPM3064ATC100-10N Altera, EPM3064ATC100-10N Datasheet - Page 5

IC MAX 3000A CPLD 64 100-TQFP

EPM3064ATC100-10N

Manufacturer Part Number
EPM3064ATC100-10N
Description
IC MAX 3000A CPLD 64 100-TQFP
Manufacturer
Altera
Series
MAX® 3000Ar
Datasheet

Specifications of EPM3064ATC100-10N

Programmable Type
In System Programmable
Delay Time Tpd(1) Max
10.0ns
Voltage Supply - Internal
3 V ~ 3.6 V
Number Of Logic Elements/blocks
4
Number Of Macrocells
64
Number Of Gates
1250
Number Of I /o
66
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
100-TQFP, 100-VQFP
Voltage
3.0 V ~ 3.6 V
Memory Type
EEPROM
Number Of Logic Elements/cells
4
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Other names
544-1974
EPM3064ATC100-10N

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Figure 1. MAX 3000A Device Block Diagram
Note:
(1)
Altera Corporation
EPM3032A, EPM3064A, EPM3128A, and EPM3256A devices have six output enables. EPM3512A devices have
10 output enables.
INPUT/OE2/GCLK2
INPUT/GCLK1
INPUT/GCLRn
INPUT/OE1
2 to 16 I/O
2 to 16 I/O
6 or 10 Output Enables (1)
Control
Control
Block
Block
I/O
I/O
Logic Array Blocks
The MAX 3000A device architecture is based on the linking of
high–performance LABs. LABs consist of 16–macrocell arrays, as shown
in
that is fed by all dedicated input pins, I/O pins, and macrocells.
Each LAB is fed by the following signals:
6 or 10
6 or 10
Figure
2 to
16
2 to
16
36 signals from the PIA that are used for general logic inputs
Global controls that are used for secondary register functions
LAB A
LAB C
1. Multiple LABs are linked together via the PIA, a global bus
Macrocells
Macrocells
33 to 48
1 to 16
MAX 3000A Programmable Logic Device Family Data Sheet
2 to 16
2 to 16
16
16
36
36
PIA
36
36
2 to 16
2 to 16
16
16
Macrocells
Macrocells
17 to 32
49 to 64
LAB D
LAB B
6 or 10 Output Enables (1)
2 to
16
2 to
16
Control
Control
Block
Block
I/O
I/O
6 or 10
6 or 10
2 to 16 I/O
2 to 16 I/O
5

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