EPM3064ATC100-10N Altera, EPM3064ATC100-10N Datasheet - Page 7

IC MAX 3000A CPLD 64 100-TQFP

EPM3064ATC100-10N

Manufacturer Part Number
EPM3064ATC100-10N
Description
IC MAX 3000A CPLD 64 100-TQFP
Manufacturer
Altera
Series
MAX® 3000Ar
Datasheet

Specifications of EPM3064ATC100-10N

Programmable Type
In System Programmable
Delay Time Tpd(1) Max
10.0ns
Voltage Supply - Internal
3 V ~ 3.6 V
Number Of Logic Elements/blocks
4
Number Of Macrocells
64
Number Of Gates
1250
Number Of I /o
66
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
100-TQFP, 100-VQFP
Voltage
3.0 V ~ 3.6 V
Memory Type
EEPROM
Number Of Logic Elements/cells
4
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Other names
544-1974
EPM3064ATC100-10N
Altera Corporation
For registered functions, each macrocell flipflop can be individually
programmed to implement D, T, JK, or SR operation with programmable
clock control. The flipflop can be bypassed for combinatorial operation.
During design entry, the designer specifies the desired flipflop type; the
Altera development system software then selects the most efficient
flipflop operation for each registered function to optimize resource
utilization.
Each programmable register can be clocked in three different modes:
Two global clock signals are available in MAX 3000A devices. As shown
in
either of the two global clock pins, GCLK1 or GCLK2.
Each register also supports asynchronous preset and clear functions. As
shown in
to control these operations. Although the product–term–driven preset
and clear from the register are active high, active–low control can be
obtained by inverting the signal within the logic array. In addition, each
register clear function can be individually driven by the active–low
dedicated global clear pin (GCLRn).
All registers are cleared upon power-up. By default, all registered outputs
drive low when the device is powered up. You can set the registered
outputs to drive high upon power-up through the Quartus
Quartus II software uses the NOT Gate Push-Back method, which uses an
additional macrocell to set the output high. To set this in the Quartus II
software, go to the Assignment Editor and set the Power-Up Level
assignment for the register to High.
Figure
Global clock signal mode, which achieves the fastest clock–to–output
performance.
Global clock signal enabled by an active–high clock enable. A clock
enable is generated by a product term. This mode provides an enable
on each flipflop while still achieving the fast clock–to–output
performance of the global clock.
Array clock implemented with a product term. In this mode, the
flipflop can be clocked by signals from buried macrocells or I/O pins.
1, these global clock signals can be the true or the complement of
Figure
2, the product–term select matrix allocates product terms
MAX 3000A Programmable Logic Device Family Data Sheet
®
II software.
7

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