EPM7064AETC100-10N Altera, EPM7064AETC100-10N Datasheet - Page 21

• Manufacturer Part Number: EPM7064AETC100-10N
• Description: IC MAX 7000 CPLD 64 100-TQFP
• Manufacturer: Altera
• Series: MAX® 7000Ar

Specifications of EPM7064AETC100-10N

• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 10.0ns
• Voltage Supply - Internal: 3 V ~ 3.6 V
• Number Of Logic Elements/blocks: 4
• Number Of Macrocells: 64
• Number Of Gates: 1250
• Number Of I /o: 68
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Voltage: 3.3V
• Memory Type: EEPROM
• Number Of Logic Elements/cells: 4
• Family Name: MAX 7000A
• # Macrocells: 64
• Number Of Usable Gates: 1250
• Frequency (max): 125MHz
• Propagation Delay Time: 10ns
• Number Of Logic Blocks/elements: 4
• # I/os (max): 68
• Operating Supply Voltage (typ): 3.3V
• In System Programmable: Yes
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: TQFP
• Cpld Type: EEPROM
• No. Of Macrocells: 64
• No. Of I/o's: 84
• Propagation Delay: 10ns
• Global Clock Setup Time: 6.2ns
• Frequency: 100MHz
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2007; EPM7064AETC100-10N

Altera Corporation
SAMPLE/PRELOAD
EXTEST
BYPASS
IDCODE
USERCODE
UESCODE
ISP Instructions
Table 8. MAX 7000A JTAG Instructions
JTAG Instruction
Allows a snapshot of signals at the device pins to be captured and examined during
normal device operation, and permits an initial data pattern output at the device pins
Allows the external circuitry and board-level interconnections to be tested by forcing a
test pattern at the output pins and capturing test results at the input pins
Places the 1-bit bypass register between the TDI and TDO pins, which allows the BST
data to pass synchronously through a selected device to adjacent devices during normal
device operation
Selects the IDCODE register and places it between the TDI and TDO pins, allowing the
IDCODE to be serially shifted out of TDO
Selects the 32-bit USERCODE register and places it between the TDI and TDO pins,
allowing the USERCODE value to be shifted out of TDO. The USERCODE instruction is
available for MAX 7000AE devices only
These instructions select the user electronic signature (UESCODE) and allow the
UESCODE to be shifted out of TDO. UESCODE instructions are available for EPM7128A
and EPM7256A devices only.
These instructions are used when programming MAX 7000A devices via the JTAG ports
with the MasterBlaster, ByteBlasterMV, or BitBlaster download cable, or using a Jam
STAPL File, JBC File, or SVF File via an embedded processor or test equipment.
MAX 7000A Programmable Logic Device Data Sheet
Description
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