EPM7064AETC100-10N Altera, EPM7064AETC100-10N Datasheet - Page 33
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EPM7064AETC100-10N
Manufacturer Part Number
EPM7064AETC100-10N
Description
IC MAX 7000 CPLD 64 100-TQFP
Manufacturer
Altera
Series
MAX® 7000Ar
Datasheet
1.EPM7032AELC44-10N.pdf
(64 pages)
Specifications of EPM7064AETC100-10N
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
10.0ns
Voltage Supply - Internal
3 V ~ 3.6 V
Number Of Logic Elements/blocks
4
Number Of Macrocells
64
Number Of Gates
1250
Number Of I /o
68
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
100-TQFP, 100-VQFP
Voltage
3.3V
Memory Type
EEPROM
Number Of Logic Elements/cells
4
Family Name
MAX 7000A
# Macrocells
64
Number Of Usable Gates
1250
Frequency (max)
125MHz
Propagation Delay Time
10ns
Number Of Logic Blocks/elements
4
# I/os (max)
68
Operating Supply Voltage (typ)
3.3V
In System Programmable
Yes
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
3.6V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
100
Package Type
TQFP
Cpld Type
EEPROM
No. Of Macrocells
64
No. Of I/o's
84
Propagation Delay
10ns
Global Clock Setup Time
6.2ns
Frequency
100MHz
Supply Voltage Range
3V To 3.6V
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2007
EPM7064AETC100-10N
EPM7064AETC100-10N
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EPM7064AETC100-10N
Manufacturer:
ALTERA30
Quantity:
82
Part Number:
EPM7064AETC100-10N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Altera Corporation
Figure 12. MAX 7000A Switching Waveforms
t
driven at 3 V for a logic
high and 0 V for a logic
low. All timing
characteristics are
measured at 1.5 V.
R
& t
F
< 2 ns. Inputs are
(Logic Array Output)
Parallel Expander
Shared Expander
Register Output
Input or I/O Pin
Register to PIA
Data or Enable
Clock into PIA
to Logic Array
Global Clock
Logic Array
Logic Array
Logic Array
Logic Array
Output Pin
at Register
PIA Delay
Clock into
Data from
Clock Pin
Input Pin
Register
Clock at
I/O Pin
Output
Global
Delay
Delay
to Pin
Input
Combinatorial Mode
Global Clock Mode
Array Clock Mode
t
t
R
R
t
t
IN
t
t
SU
IN
IO
t
MAX 7000A Programmable Logic Device Data Sheet
t
ACH
CH
t
t
H
t
t
t
GLOB
PIA
IN
IO
t
RD
t
t
IC
SU
t
PIA
t
t
ACL
t
CL
SEXP
t
H
t
PIA
t
OD
t
LAC
, t
LAD
t
PEXP
t
t
F
F
t
COMB
t
CLR
, t
PRE
t
OD
t
OD
t
PIA
33