EPM7064AETC100-10N Altera, EPM7064AETC100-10N Datasheet - Page 55

• Manufacturer Part Number: EPM7064AETC100-10N
• Description: IC MAX 7000 CPLD 64 100-TQFP
• Manufacturer: Altera
• Series: MAX® 7000Ar

Specifications of EPM7064AETC100-10N

• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 10.0ns
• Voltage Supply - Internal: 3 V ~ 3.6 V
• Number Of Logic Elements/blocks: 4
• Number Of Macrocells: 64
• Number Of Gates: 1250
• Number Of I /o: 68
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Voltage: 3.3V
• Memory Type: EEPROM
• Number Of Logic Elements/cells: 4
• Family Name: MAX 7000A
• # Macrocells: 64
• Number Of Usable Gates: 1250
• Frequency (max): 125MHz
• Propagation Delay Time: 10ns
• Number Of Logic Blocks/elements: 4
• # I/os (max): 68
• Operating Supply Voltage (typ): 3.3V
• In System Programmable: Yes
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: TQFP
• Cpld Type: EEPROM
• No. Of Macrocells: 64
• No. Of I/o's: 84
• Propagation Delay: 10ns
• Global Clock Setup Time: 6.2ns
• Frequency: 100MHz
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2007; EPM7064AETC100-10N

Altera Corporation
The parameters in this equation are:
MC
MC
MC
f
tog
A, B, C
This calculation provides an I
using a pattern of a 16-bit, loadable, enabled, up/down counter in each
LAB with no output load. Actual I
because this measurement is sensitive to the actual pattern in the device
and the environmental operating conditions.
MAX
Table 31. MAX 7000A I
LC
TON
DEV
USED
EPM7032AE
EPM7064AE
EPM7128A
EPM7128AE
EPM7256A
EPM7256AE
EPM7512AE
Device
= Number of macrocells with the Turbo Bit option turned
= Number of macrocells in the device
= Total number of macrocells in the design, as reported in
= Highest clock frequency to the device
= Average percentage of logic cells toggling at each clock
= Constants, shown in
on, as reported in the MAX+PLUS II Report File (.rpt)
the Report File
(typically 12.5%)
CC
MAX 7000A Programmable Logic Device Data Sheet
Equation Constants
CC
0.71
0.71
0.71
0.71
0.71
0.71
0.71
estimate based on typical conditions
A
CC
Table 31
should be verified during operation
0.30
0.30
0.30
0.30
0.30
0.30
0.30
B
0.014
0.014
0.014
0.014
0.014
0.014
0.014
C
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