EPM7064AETC100-10N Altera, EPM7064AETC100-10N Datasheet - Page 38
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EPM7064AETC100-10N
Manufacturer Part Number
EPM7064AETC100-10N
Description
IC MAX 7000 CPLD 64 100-TQFP
Manufacturer
Altera
Series
MAX® 7000Ar
Datasheet
1.EPM7032AELC44-10N.pdf
(64 pages)
Specifications of EPM7064AETC100-10N
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
10.0ns
Voltage Supply - Internal
3 V ~ 3.6 V
Number Of Logic Elements/blocks
4
Number Of Macrocells
64
Number Of Gates
1250
Number Of I /o
68
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
100-TQFP, 100-VQFP
Voltage
3.3V
Memory Type
EEPROM
Number Of Logic Elements/cells
4
Family Name
MAX 7000A
# Macrocells
64
Number Of Usable Gates
1250
Frequency (max)
125MHz
Propagation Delay Time
10ns
Number Of Logic Blocks/elements
4
# I/os (max)
68
Operating Supply Voltage (typ)
3.3V
In System Programmable
Yes
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
3.6V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
100
Package Type
TQFP
Cpld Type
EEPROM
No. Of Macrocells
64
No. Of I/o's
84
Propagation Delay
10ns
Global Clock Setup Time
6.2ns
Frequency
100MHz
Supply Voltage Range
3V To 3.6V
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2007
EPM7064AETC100-10N
EPM7064AETC100-10N
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EPM7064AETC100-10N
Manufacturer:
ALTERA30
Quantity:
82
Part Number:
EPM7064AETC100-10N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
MAX 7000A Programmable Logic Device Data Sheet
38
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Symbol
IN
IO
FIN
SEXP
PEXP
LAD
LAC
IOE
OD1
OD2
OD3
ZX1
ZX2
ZX3
XZ
SU
H
FSU
FH
RD
COMB
IC
Table 20. EPM7064AE Internal Timing Parameters (Part 1 of 2)
Input pad and buffer delay
I/O input pad and buffer
delay
Fast input delay
Shared expander delay
Parallel expander delay
Logic array delay
Logic control array delay
Internal output enable delay
Output buffer and pad
delay, slow slew rate = off
V
Output buffer and pad
delay, slow slew rate = off
V
Output buffer and pad
delay, slow slew rate = on
V
Output buffer enable delay,
slow slew rate = off
V
Output buffer enable delay,
slow slew rate = off
V
Output buffer enable delay,
slow slew rate = on
V
Output buffer disable delay C1 = 5 pF
Register setup time
Register hold time
Register setup time of fast
input
Register hold time of fast
input
Register delay
Combinatorial delay
Array clock delay
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
= 3.3 V
= 2.5 V
= 2.5 V or 3.3 V
= 3.3 V
= 2.5 V
= 3.3 V
Parameter
C1 = 35 pF
C1 = 35 pF
(5)
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
(5)
C1 = 35 pF
Conditions
Min
1.3
0.6
1.0
1.5
-4
Max
0.6
0.6
2.5
1.8
0.4
1.5
0.6
0.0
0.8
1.3
5.8
4.0
4.5
9.0
4.0
0.7
0.6
1.2
Note (1)
Speed Grade
Min
2.0
1.0
1.5
1.5
-7
Max
1.1
1.1
3.0
3.0
0.7
2.5
1.0
0.0
1.3
1.8
6.3
4.0
4.5
9.0
4.0
1.2
0.9
1.9
Altera Corporation
Min
2.9
1.3
1.5
1.5
-10
Max
10.0
1.2
1.4
1.4
3.7
3.9
0.9
3.2
0.0
1.8
2.3
6.8
5.0
5.5
5.0
1.6
1.3
2.5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns