EPM3512AFC256-10 Altera, EPM3512AFC256-10 Datasheet - Page 15
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EPM3512AFC256-10
Manufacturer Part Number
EPM3512AFC256-10
Description
IC MAX 3000A CPLD 512 256-FBGA
Manufacturer
Altera
Series
MAX® 3000Ar
Datasheet
1.EPM3032ATC44-10N.pdf
(46 pages)
Specifications of EPM3512AFC256-10
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
10.0ns
Voltage Supply - Internal
3 V ~ 3.6 V
Number Of Logic Elements/blocks
32
Number Of Macrocells
512
Number Of Gates
10000
Number Of I /o
208
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
256-FBGA
Voltage
3.0 V ~ 3.6 V
Memory Type
EEPROM
Number Of Logic Elements/cells
32
Family Name
MAX 3000A
# Macrocells
512
Number Of Usable Gates
10000
Frequency (max)
125MHz
Propagation Delay Time
10ns
Number Of Logic Blocks/elements
32
# I/os (max)
208
Operating Supply Voltage (typ)
3.3V
In System Programmable
Yes
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
3.6V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
256
Package Type
FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-2279
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EPM3512AFC256-10
Manufacturer:
ALTERA
Quantity:
59
Company:
Part Number:
EPM3512AFC256-10
Manufacturer:
ALTERA
Quantity:
917
Part Number:
EPM3512AFC256-10
Manufacturer:
ALTERA
Quantity:
20 000
Company:
Part Number:
EPM3512AFC256-10N
Manufacturer:
ALTERA
Quantity:
13
Company:
Part Number:
EPM3512AFC256-10N
Manufacturer:
ALTERA
Quantity:
917
Part Number:
EPM3512AFC256-10N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Altera Corporation
By combining the pulse and shift times for each of the programming
stages, the program or verify time can be derived as a function of the TCK
frequency, the number of devices, and specific target device(s). Because
different ISP-capable devices have a different number of EEPROM cells,
both the total fixed and total variable times are unique for a single device.
Programming a Single MAX 3000A Device
The time required to program a single MAX 3000A device in-system can
be calculated from the following formula:
where: t
The ISP times for a stand-alone verification of a single MAX 3000A device
can be calculated from the following formula:
where: t
t
t
PROG
VER
=
=
t
VPULSE
t
Cycle
f
t
Cycle
TCK
t
PROG
PPULSE
VER
VPULSE
PPULSE
PTCK
VTCK
+
MAX 3000A Programmable Logic Device Family Data Sheet
+
Cycle
--------------------------------
Cycle
------------------------------- -
= Programming time
= Sum of the fixed times to erase, program, and
= Number of TCK cycles to program a device
= TCK frequency
f
= Verify time
= Sum of the fixed times to verify the EEPROM cells
= Number of TCK cycles to verify a device
TCK
f
TCK
VTCK
verify the EEPROM cells
PTCK
15