EPM3512AFC256-10 Altera, EPM3512AFC256-10 Datasheet - Page 27
![IC MAX 3000A CPLD 512 256-FBGA](/photos/6/70/67063/544-256-fbga_sml.jpg)
EPM3512AFC256-10
Manufacturer Part Number
EPM3512AFC256-10
Description
IC MAX 3000A CPLD 512 256-FBGA
Manufacturer
Altera
Series
MAX® 3000Ar
Datasheet
1.EPM3032ATC44-10N.pdf
(46 pages)
Specifications of EPM3512AFC256-10
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
10.0ns
Voltage Supply - Internal
3 V ~ 3.6 V
Number Of Logic Elements/blocks
32
Number Of Macrocells
512
Number Of Gates
10000
Number Of I /o
208
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
256-FBGA
Voltage
3.0 V ~ 3.6 V
Memory Type
EEPROM
Number Of Logic Elements/cells
32
Family Name
MAX 3000A
# Macrocells
512
Number Of Usable Gates
10000
Frequency (max)
125MHz
Propagation Delay Time
10ns
Number Of Logic Blocks/elements
32
# I/os (max)
208
Operating Supply Voltage (typ)
3.3V
In System Programmable
Yes
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
3.6V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
256
Package Type
FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-2279
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EPM3512AFC256-10
Manufacturer:
ALTERA
Quantity:
59
Company:
Part Number:
EPM3512AFC256-10
Manufacturer:
ALTERA
Quantity:
917
Part Number:
EPM3512AFC256-10
Manufacturer:
ALTERA
Quantity:
20 000
Company:
Part Number:
EPM3512AFC256-10N
Manufacturer:
ALTERA
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13
Company:
Part Number:
EPM3512AFC256-10N
Manufacturer:
ALTERA
Quantity:
917
Part Number:
EPM3512AFC256-10N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Figure 11. MAX 3000A Switching Waveforms
Altera Corporation
t
driven at 3 V for a logic
high and 0 V for a logic
low. All timing
characteristics are
measured at 1.5 V.
R
& t
F
< 2 ns. Inputs are
(Logic Array Output)
Parallel Expander
Shared Expander
Register Output
Input or I/O Pin
Register to PIA
Data or Enable
Clock into PIA
to Logic Array
Global Clock
Logic Array
Logic Array
Logic Array
Logic Array
Output Pin
at Register
PIA Delay
Clock into
Data from
Input Pin
Clock Pin
Register
Clock at
I/O Pin
Output
Global
Delay
Delay
to Pin
Input
Combinatorial Mode
Global Clock Mode
Array Clock Mode
t
t
R
R
MAX 3000A Programmable Logic Device Family Data Sheet
t
t
IN
t
t
SU
IN
IO
t
t
ACH
CH
t
t
t
t
H
t
PIA
IN
GLOB
IO
t
RD
t
t
IC
SU
t
PIA
t
t
ACL
t
CL
SEXP
t
H
t
PIA
t
OD
t
LAC
, t
LAD
t
PEXP
t
t
F
F
t
COMB
t
CLR
, t
PRE
t
OD
t
OD
t
PIA
27