ADSP-2184NKCA-320 Analog Devices Inc, ADSP-2184NKCA-320 Datasheet - Page 40

• Manufacturer Part Number: ADSP-2184NKCA-320
• Description: IC DSP 16BIT 80MHZ 144CSPBGA
• Manufacturer: Analog Devices Inc
• Series: ADSP-21xxr
• Type: Fixed Pointr

Specifications of ADSP-2184NKCA-320

• Rohs Status: RoHS non-compliant
• Interface: Host Interface, Serial Port
• Clock Rate: 80MHz
• Non-volatile Memory: External
• On-chip Ram: 20kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.80V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 144-CSPBGA
• Device Core Size: 16b
• Architecture: Enhanced Harvard
• Format: Fixed Point
• Clock Freq (max): 80MHz
• Mips: 80
• Device Input Clock Speed: 80MHz
• Ram Size: 20KB
• Program Memory Size: Not RequiredKB
• Operating Supply Voltage (typ): 1.8/2.5/3.3V
• Operating Supply Voltage (min): 1.71V
• Operating Supply Voltage (max): 1.89/3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: CSPBGA
• Package: 144CSP-BGA
• Numeric And Arithmetic Format: Fixed-Point
• Maximum Speed: 80 MHz
• Device Million Instructions Per Second: 80 MIPS
• Lead Free Status / Rohs Status: Not Compliant

ADSP-218xN
LQFP PACKAGE PINOUT
The LQFP package pinout is shown
Pin names in bold text in the table replace the plain-text-named
functions when Mode C = 1. A + sign separates two functions
when either function can be active for either major I/O mode.
Signals enclosed in brackets [ ] are state bits latched from the
A11/IAD10
A12/IAD11
A13/IAD12
A10/IAD9
CLKOUT
A4/IAD3
A5/IAD4
A6/IAD5
A7/IAD6
A8/IAD7
A9/IAD8
V
V
CLKIN
DDEXT
XTAL
DDINT
IOMS
GND
GND
GND
BMS
DMS
CMS
PMS
WR
RD
24
10
11
12
13
14
15
16
17
18
19
20
21
22
23
25
1
3
2
4
5
6
7
8
9
Figure 38
PIN 1
IDENTIFIER
and in
Figure 38. 100-Lead LQFP Pin Configuration
Rev. A | Page 40 of 48 | August 2006
Table
27.
ADSP-218xN
(Not to Scale)
TOP VIEW
value of the pin at the deassertion of RESET. The multiplexed
pins DT1/FO, TFS1/IRQ1, RFS1/IRQ0, and DR1/FI, are mode
selectable by setting Bit 10 (SPORT1 configure) of the System
Control Register. If Bit 10 = 1, these pins have serial port func-
tionality. If Bit 10 = 0, these pins are the external interrupt and
flag pins. This bit is set to 1 by default, upon reset.
72
71
70
64
59
58
57
56
55
54
53
52
51
75
74
73
69
68
67
66
65
63
62
61
60
D15
D14
D13
D12
GND
D11
D10
D9
V
GND
D8
D7/IWR
D6/IRD
D5/IAL
D4/IS
GND
V
D3/IACK
D2/IAD15
D1/IAD14
D0/IAD13
BG
EBG
BR
EBR
DDEXT
DD INT