ADSP-21262SKBCZ200 Analog Devices Inc, ADSP-21262SKBCZ200 Datasheet - Page 17

• Manufacturer Part Number: ADSP-21262SKBCZ200
• Description: IC DSP CTLR 32BIT 136CSPBGA
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Fixed/Floating Pointr

Specifications of ADSP-21262SKBCZ200

• Interface: DAI, SPI
• Clock Rate: 200MHz
• Non-volatile Memory: ROM (512 kB)
• On-chip Ram: 256kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.20V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 136-CSPBGA
• No. Of Bits: 32 Bit
• Frequency: 200MHz
• Supply Voltage: 1.2V
• Embedded Interface Type: SPI
• No. Of I/o's: 23
• Supply Voltage Range: 1.14V To 1.26V, 3.13V To 3.47V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADSP21262SKBCZ200

TIMING SPECIFICATIONS
The ADSP-21262’s internal clock (a multiple of CLKIN) pro-
vides the clock signal for timing internal memory, processor
core, serial ports, and parallel port (as required for read/write
strobes in asynchronous access mode). During reset, program
the ratio between the DSP’s internal clock frequency and exter-
nal (CLKIN) clock frequency with the CLKCFG1–0 pins. To
determine switching frequencies for the serial ports, divide
down the internal clock, using the programmable divider con-
trol of each port (DIVx for the serial ports).
The ADSP-21262’s internal clock switches at higher frequencies
than the system input clock (CLKIN). To generate the internal
clock, the DSP uses an internal phase-locked loop (PLL). This
PLL-based clocking minimizes the skew between the system
clock (CLKIN) signal and the DSP’s internal clock (the clock
source for the parallel port logic and I/O pads).
Note the definitions of various clock periods that are a function
of CLKIN and the appropriate ratio control
Table
Table 7. ADSP-21262 CLKOUT and CCLK Clock
Generation Operation
Table 8. Clock Periods
1
Figure 5
external oscillator or crystal. Note that more ratios are possible
and can be set through software using the power management
control register (PMCTL). For more information, see the
ADSP-2126x SHARC DSP Core Manual.
Use the exact timing information given. Do not attempt to
derive parameters from the addition or subtraction of others.
While addition or subtraction would yield meaningful results
for an individual device, the values given in this data sheet
reflect statistical variations and worst cases. Consequently, it is
not meaningful to add parameters to derive longer times.
See
reference levels.
Timing Requirements
CLKIN
CCLK
Timing
Requirements
t
t
t
t
where:
SR = serial port-to-core clock ratio (wide range, determined by SPORT
CK
CCLK
SCLK
SPICLK
CLKDIV)
SPIR = SPI-to-core clock ratio (wide range, determined by SPIBAUD
register)
DAI_Px = serial port clock
SPICLK = SPI clock
Figure 30 on Page 38
8).
shows core to CLKIN ratios of 3:1, 8:1, and 16:1 with
Description
CLKIN Clock Period
(Processor) Core Clock Period
Serial Port Clock Period = (t
SPI Clock Period = (t
under Test Conditions for voltage
Description
Input Clock
Core Clock
1
CCLK
(Table 7
) × SPIR
Calculation
1/t
1/t
CK
CCLK
CCLK
Rev. B | Page 17 of 48 | August 2005
) × SR
and
Switching characteristics specify how the processor changes its
signals. Circuitry external to the processor must be designed for
compatibility with these signal characteristics. Switching char-
acteristics describe what the processor will do in a given
circumstance. Use switching characteristics to ensure that any
timing requirement of a device connected to the processor (such
as memory) is satisfied.
Timing requirements apply to signals that are controlled by cir-
cuitry external to the processor, such as the data input for a read
operation. Timing requirements guarantee that the processor
operates correctly with other devices.
XTAL
CLKIN
Figure 5. Core Clock and System Clock Relationship to CLKIN
XTAL
OSC
PLLICLK
CLKCFG1–0
3:1, 8:1,
16:1
PLL
ADSP-21262
CCLK
(CORE CLOCK)
CLKOUT