DSPB56724AG Freescale Semiconductor, DSPB56724AG Datasheet - Page 11

• Manufacturer Part Number: DSPB56724AG
• Description: DSP 24BIT AUD 250MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: Symphony™r
• Type: Audio Processorr

Specifications of DSPB56724AG

• Interface: Host Interface, I²C, SAI, SPI
• Clock Rate: 250MHz
• Non-volatile Memory: External
• On-chip Ram: 112kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.20V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 6
1.1.9
Table 7
Freescale Semiconductor
Note:
1. Measured at 50% of the input transition.
2. The indicated duty cycle is for the specified maximum frequency for which a part is rated. The minimum clock high or low time
3. Maximum frequency of 200 MHz supported at 0.95 V < V
4. PLL
No.
required for correct operation, however, remains the same at lower operating frequencies; therefore, when a lower clock
frequency is used, the signal symmetry may vary from the specified duty cycle as long as the minimum high time and low
time requirements are met.
Maximum frequency of 250 MHz supported at 1.14 V < V
10
11
13
14
15
16
17
18
No.
6
7
8
9
LOCK
lists the clock operation.
lists the reset, stop, mode select, and interrupt timing.
Delay from RESET assertion to all pins at reset value
Required RESET duration
Syn reset deassert delay time
Mode select setup time
Mode select hold time
Minimum edge-triggered interrupt request assertion width
Minimum edge-triggered interrupt request deassertion width
Delay from interrupt trigger to interrupt code execution
• Power on, external clock generator, PLL disabled
• Power on, external clock generator, PLL enabled
• Minimum
• Maximum (PLL enabled)
EXTAL input high
(40% to 60% duty cycle)
EXTAL input low
(40% to 60% duty cycle)
EXTAL cycle time
Instruction cycle time
• Crystal oscillator
• Square wave input
• Crystal oscillator
• Square wave input
• With PLL disabled
• With PLL enabled
• With PLL disabled
• With PLL enabled
= 200 μs.
Reset, Stop, Mode Select, and Interrupt Timing
Symphony
Characteristics
1
1
Table 7. Reset, Stop, Mode Select, and Interrupt Timing
Characteristics
4
™
DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 2
Table 6. Clock Operation
VDD_CORE
VDD_CORE
3
Symbol
Eth
Etc
Etl
Tc
< 1.05 V and –40 < Tj < 100° C
< 1.26 V and 0 < Tj < 90° C
(2xT
Expression
16.67
16.67
10 × T
33.3
Min
2.5
2.5
4
C
5
5
2 × T
2 × T
2 × T
4
)+PLL
—
—
—
—
—
C + 4
C
C
C
LOCK
5120
Max
100
100
500
inf
inf
inf
inf
Min
200
10
10
10
10
12
54
—
7
4
Max
11
—
—
—
—
—
—
—
—
—
Units
ns
ns
ns
ns
Unit
ns
ns
ns
ns
us
ns
ns
ns
ns
ns
11