DSPB56724AG Freescale Semiconductor, DSPB56724AG Datasheet - Page 23

• Manufacturer Part Number: DSPB56724AG
• Description: DSP 24BIT AUD 250MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: Symphony™r
• Type: Audio Processorr

Specifications of DSPB56724AG

• Interface: Host Interface, I²C, SAI, SPI
• Clock Rate: 250MHz
• Non-volatile Memory: External
• On-chip Ram: 112kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.20V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Note:
1. V
2. Pull-up resistor: R
3. Capacitive load: C
5. All times assume noise free inputs
5. All times assume internal clock frequency of 200 MHz
6. SHI_1 specs match those of SHI
7. The numbers listed are based on the module/pad design and its characteristics during output. The module is compliant with
1.2.3
The programmed serial clock cycle, T
control register).
The expression for T
where
In I
to
The programmed serial clock cycle (T
shown in next.
Freescale Semiconductor
No.
60
61
I
2
2
CORE_VDD
C standard, so the module should receive I
C mode, the user may select a value for the programmed serial clock cycle from
HREQ in assertion to first SCL edge
First SCL edge to HREQ is not asserted
(HREQ in hold time.)
• Filters bypassed
• Very Narrow filters enabled
• Narrow filters enabled
• Wide filters enabled
T
— HRS is the prescaler rate select bit. When HRS is cleared, the fixed
— HDM[7:0] are the divider modulus select bits. A divide ratio from 1 to 256 (HDM[7:0] = $00 to $FF) may be
I
2
CCP
divide-by-eight prescaler is operational. When HRS is set, the prescaler is bypassed.
selected.
Programming the SHI I
= 1.00± 0.05 V; T
+ 3 × T
Characteristics
P
I
b
2
CCP
(min) = 1.5 kΩ
(max) = 50 pF
C
Symphony
+ 45ns + T
is
T
I
2
CCP
J
= –40° C to 100° C, C
4096 × T
6 × T
Table 10. SHI I
= [T
™
1,2,3,4,5
I
R
I
2
2
DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 2
CCP
CCP
C
C
× 2 × (HDM[7:0] + 1) × (7 × (1 – HRS) + 1)]
, is specified by the value of the HDM[7:0] and HRS bits of the HCKR (SHI clock
) should be chosen in order to achieve the desired SCL serial clock cycle (T
C
(Nominal, SCL Serial Clock Cycle (TSCL) generated as master)
(if HDM[7:0] = $02 and HRS = 1)
2
(if HDM[7:0] = $FF and HRS = 0)
C bus compliant signal without any issue.
2
2
C Serial Clock
C Protocol Timing (Continued)
L
Standard I
= 50 pF
Expression
Symbol/
T
t
HO;RQI
AS;RQI
2
C
4327
4317
4282
4227
Min
0.0
Standard
Max
—
—
—
—
—
Min
927
917
877
827
0.0
Fast-Mode
Max
—
—
—
—
—
SCL
Eqn. 4
Eqn. 5
Eqn. 6
Eqn. 7
Unit
), as
ns
ns
ns
ns
ns
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