DSPB56720CAG Freescale Semiconductor, DSPB56720CAG Datasheet - Page 10

• Manufacturer Part Number: DSPB56720CAG
• Description: DSP 24BIT AUD 200MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: Symphony™r
• Type: Audio Processorr

Specifications of DSPB56720CAG

• Interface: Host Interface, I²C, SAI, SPI
• Clock Rate: 200MHz
• Non-volatile Memory: External
• On-chip Ram: 744kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.00V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Device Core Size: 24b
• Format: Fixed Point
• Clock Freq (max): 200MHz
• Mips: 200
• Device Input Clock Speed: 200MHz
• Program Memory Size: Not RequiredKB
• Operating Supply Voltage (typ): 1/3.3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

P
T
2.3
To prevent high current conditions due to possible improper sequencing of the power supplies, use an external Schottky diode
as shown in
If an external Schottky diode is not used (to prevent a high current condition at power-up), then IO_VDD must be applied ahead
of Core_VDD, as shown in
For correct operation of the internal power-on reset logic, the Core_VDD ramp rate (Tr) to full supply must be less than 10 ms,
as shown in
There are no power down requirement for the digital 1.0 V (CORE) and 3.3 V (IO). For the analog PLL power, the digital (IO)
3.3 V must be power up before the analog 3.3 V power. Similarly, for power down the digital (IO) 3.3 V must be power down
after the analog power 3.3 V. This requirement is for avoiding possible leakage.
10
D
J
= 0.6875 W
= 97.5° C
=
=
70
1.1 V × 625 mA
+ (
0.6875 × 40
Power Requirements
Figure
Figure
Figure 8. Ensure Correct Operation of Power-On Reset with Fast Ramp of Core_VDD
Figure 7. Prevent High Current Conditions by Applying IO_VDD Before Core_VDD
Figure 6. Prevent High Current Conditions by Using External Schottky Diode
6, connected between the DSP56720/DSP56721 IO_VDD and Core_VDD power pins.
8.
)
Symphony
Figure
IO_VDD
Core_VDD
7.
Core_VDD
™
DSP56720/DSP56721 Multi-Core Audio Processors, Rev. 5
Core_VDD
0 V
IO_VDD
Tr must be < 10 ms
Tr
Schottky
External
Diode
1.0 V
Freescale Semiconductor