DSPB56720CAG Freescale Semiconductor, DSPB56720CAG Datasheet - Page 15

• Manufacturer Part Number: DSPB56720CAG
• Description: DSP 24BIT AUD 200MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: Symphony™r
• Type: Audio Processorr

Specifications of DSPB56720CAG

• Interface: Host Interface, I²C, SAI, SPI
• Clock Rate: 200MHz
• Non-volatile Memory: External
• On-chip Ram: 744kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.00V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Device Core Size: 24b
• Format: Fixed Point
• Clock Freq (max): 200MHz
• Mips: 200
• Device Input Clock Speed: 200MHz
• Program Memory Size: Not RequiredKB
• Operating Supply Voltage (typ): 1/3.3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2.9
Table 7
Freescale Semiconductor
No.
10
11
13
14
15
16
17
18
19
20
21
shows the reset, stop, mode select, and interrupt timing.
Delay from RESET assertion to all pins at reset value
Required RESET duration
Syn reset deassert delay time
Mode select setup time
Mode select hold time
Minimum edge-triggered interrupt request assertion width
Minimum edge-triggered interrupt request deassertion width
Delay from interrupt trigger to interrupt code execution
Duration of level sensitive IRQA assertion to ensure interrupt service
(when exiting Stop)
Interrupt Requests Rate
• Power on, external clock generator, PLL disabled
• Power on, external clock generator, PLL enabled
• Minimum
• Maximum (PLL enabled)
• PLL is active during Stop and Stop delay is enabled (OMR Bit 6 = 0)
• PLL is active during Stop and Stop delay is not enabled (OMR Bit 6 =
• PLL is not active during Stop and Stop delay is enabled (OMR Bit 6 =
• PLL is not active during Stop and Stop delay is not enabled (OMR Bit
• Delay from IRQA, IRQB, IRQC, IRQD, NMI assertion to
• ESAI, ESAI_1, ESAI_2, ESAI_3, SHI, SHI_1, Timer, Timer_1
• DMA
• IRQ, NMI (edge trigger)
• IRQ (level trigger)
Reset, Stop, Mode Select, and Interrupt Timing
1)
0)
6 = 1)
general-purpose transfer output valid caused by first interrupt
instruction execution
Table 7. Reset, Stop, Mode Select, and Interrupt Timing Parameters
Symphony
1, 2, 3
1
1
4
Characteristics
™
DSP56720/DSP56721 Multi-Core Audio Processors, Rev. 5
3
(128 Kbytes × T
(128 Kbytes × T
(25 × T
(2 x T
10 × T
Expression
10 × T
25 × T
12 × T
12 × T
2 × T
2 × T
2 × T
T
8 × T
8 × T
C
C
LOCK
—
) + T
—
—
—
—
) + T
C
C + 4
+ 3.8
C
C
C
C
C
C
C
C
LOCK
LOCK
C
C)
) +
10.0
Min
200
655
125
855
200
10
10
10
12
54
—
—
—
—
—
—
7
4
Max
53.8
60.0
40.0
40.0
60.0
11
—
—
—
—
—
—
—
—
—
—
—
—
—
Unit
ns
ns
ns
ns
us
ns
ns
ns
ns
ns
μs
ns
μs
μs
ns
ns
ns
ns
ns
15