DSPB56720CAG Freescale Semiconductor, DSPB56720CAG Datasheet - Page 29

• Manufacturer Part Number: DSPB56720CAG
• Description: DSP 24BIT AUD 200MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: Symphony™r
• Type: Audio Processorr

Specifications of DSPB56720CAG

• Interface: Host Interface, I²C, SAI, SPI
• Clock Rate: 200MHz
• Non-volatile Memory: External
• On-chip Ram: 744kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.00V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Device Core Size: 24b
• Format: Fixed Point
• Clock Freq (max): 200MHz
• Mips: 200
• Device Input Clock Speed: 200MHz
• Program Memory Size: Not RequiredKB
• Operating Supply Voltage (typ): 1/3.3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Freescale Semiconductor
Notes:
1. V
2. i ck = internal clock
3. bl = bit length
4. SCKT(SCKT pin) = transmit clock
5. For the internal clock, the external clock cycle is defined by Tc and the ESAI control register.
6. The word-relative frame sync signal waveform relative to the clock operates in the same manner as the bit-length frame sync
7. Periodically sampled and not 100% tested.
8. ESAI_1, ESAI_2, ESAI_3 specs match those of ESAI.
No.
92
93
94
95
96
97
x ck = external clock
i ck a = internal clock, asynchronous mode
(Asynchronous implies that SCKT and SCKR are two different clocks.)
i ck s = internal clock, synchronous mode
(Synchronous implies that SCKT and SCKR are the same clock.)
wl = word length
wr = word length relative
SCKR(SCKR pin) = receive clock
FST(FST pin) = transmit frame sync
FSR(FSR pin) = receive frame sync
HCKT(HCKT pin) = transmit high frequency clock
HCKR(HCKR pin) = receive high frequency clock
signal waveform, but spreads from one serial clock before first bit clock (same as bit length frame sync signal), until the one
before last bit clock of the first word in frame.
CORE_VDD
FST input (wl) to data out enable from high impedance
FST input (wl) to transmitter #0 drive enable assertion
Flag output valid after SCKT rising edge
HCKR/HCKT clock cycle
HCKT input rising edge to SCKT output
HCKR input rising edge to SCKR output
= 1.00 ± 0.10 V; T
Table 10. Enhanced Serial Audio Interface Timing Parameters (Continued)
Characteristics
Symphony
J
= –40°C to 100°C; C
™
DSP56720/DSP56721 Multi-Core Audio Processors, Rev. 5
1, 3, 4
L
= 50 pF.
Symbol
—
—
—
—
—
—
Expression
2 × T
—
—
—
—
—
C
5
Min
10
—
—
—
—
—
—
Max
21.0
14.0
14.0
18.0
18.0
9.0
—
Condition
x ck
i ck
—
—
—
—
—
2
Unit
ns
ns
ns
ns
ns
ns
29