ADMCF341BR Analog Devices Inc, ADMCF341BR Datasheet - Page 13

• Manufacturer Part Number: ADMCF341BR
• Description: IC DSP 3CH 12BIT MOT-CTRL 28SOIC
• Manufacturer: Analog Devices Inc
• Series: Motor Controlr
• Type: Motor Controlr

Specifications of ADMCF341BR

• Rohs Status: RoHS non-compliant
• Interface: Synchronous Serial Port (SSP)
• Clock Rate: 20MHz
• Non-volatile Memory: FLASH (12 kB), ROM (12kB)
• On-chip Ram: 2.5kB
• Voltage - I/o: 5.00V
• Voltage - Core: 5.00V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (7.5mm Width)

The PWMDT register is a 10-bit register. For a CLKOUT
rate of 20 MHz its maximum value of 0x3FF (= 1023) corre-
sponds to a maximum programmed dead time of:
The dead time can be programmed to zero by writing 0 to the
PWMDT register.
PWM Operating Mode: MODECTRL and
SYSSTAT Registers
The PWM controller of the ADMC(F)341 can operate in two
distinct modes: single update mode and double update mode.
The operating mode of the PWM controller is determined by
the state of Bit 6 of the MODECTRL register. If this bit is
cleared, the PWM operates in the single update mode. Setting
Bit 6 places the PWM in the double update mode. By default,
following either a peripheral reset or power-on, Bit 6 of the
MODECTRL register is cleared. This means that the default
operating mode is single update mode.
In single update mode, a single PWMSYNC pulse is produced
in each PWM period. The rising edge of this signal marks the
start of a new PWM cycle and is used to latch new values from
the PWM configuration registers (PWMTM, PWMDT, PWMPD,
and PWMSYNCWT) and the PWM duty cycle registers
(PWMCHA, PWMCHB, and PWMCHC) into the three-phase
timing unit. The PWMSEG register is also latched into the
output control unit on the rising edge of the PWMSYNC pulse.
In effect, this means that the parameters of the PWM signals
can be updated only once per PWM period at the start of each
cycle. Thus, the generated PWM patterns are symmetrical,
centered around the midpoint of the switching period.
In double update mode, there is an additional PWMSYNC
pulse produced at the midpoint of each PWM period. The
rising edge of this new PWMSYNC pulse is again used to latch
new values of the PWM configuration registers, duty cycle
registers, and the PWMSEG register. As a result, it is possible
to alter both the characteristics (switching frequency, dead time,
minimum pulse width, and PWMSYNC pulse width) and the
output duty cycles at the midpoint of each PWM cycle. Conse-
quently, it is possible to produce PWM switching patterns that
are no longer symmetrical, centered around the midpoint of the
period (asymmetrical PWM patterns).
In double update mode, operation in the first half or the second
half of the PWM cycle is indicated by Bit 3 of the SYSSTAT
register. In double update mode, this bit is cleared during
operation in the first half of each PWM period (between the
rising edge of the original PWMSYNC pulse and the rising edge
of the new PWMSYNC pulse, which is introduced in double
update mode). Bit 3 of the SYSSTAT register is set during the
second half of each PWM period. If required, a user may
determine the status of this bit during a PWMSYNC interrupt
service routine.
REV. B
T
D
max
=
=
=
1023 2
1023 2 50 10
102
µ
× ×
× ×
s
t
CK
×
−
9
sec
–13–
The advantages of double update mode are that lower harmonic
voltages can be produced by the PWM process and wider
control bandwidths are possible. However, for a given PWM
switching frequency, the PWMSYNC pulses occur at twice the
rate in the double update mode. Because new duty cycle values
must be computed in each PWMSYNC interrupt service rou-
tine, there is a larger computational burden on the DSP in
double update mode.
Width of the PWMSYNC Pulse: PWMSYNCWT Register
The PWM controller of the ADMC(F)341 produces an internal
PWM synchronization pulse at a rate equal to the PWM switching
frequency in single update mode and at twice the PWM fre-
quency in double update mode. This PWMSYNC synchronizes
the operation of the PWM unit with the A/D converter system.
The width of this PWMSYNC pulse is programmable by the
PWMSYNCWT register. The width of the PWMSYNC pulse,
T
which means that the width of the pulse is programmable from
t
rate of 20 MHz). Following a reset, the PWMSYNCWT
register contains 0x27 (= 39) so that the default PWMSYNC
width is 2.0 µs.
PWM Duty Cycles: PWMCHA, PWMCHB, PWMCHC
Registers
The duty cycles of the six PWM output signals are controlled
by the three duty cycle registers, PWMCHA, PWMCHB, and
PWMCHC. The integer value in the register PWMCHA con-
trols the duty cycle of the signals on AH and AL. PWMCHB
controls the duty cycle of the signals on BH and BL, and
PWMCHC controls the duty cycle of the signals on CH and
CL. The duty cycle registers are programmed in integer counts
of the fundamental time unit, t
of the high-side PWM signal produced by the three-phase timing
unit over half the PWM period. The switching signals produced
by the three-phase timing unit are also adjusted to incorporate
the programmed dead time value in the PWMDT register.
The PWM is center-based. This means that in single update
mode, the resulting output waveforms are symmetrical and
centered in the PWMSYNC period. Figure 7 presents a typical
PWM timing diagram illustrating the PWM-related registers’
(PWMCHA, PWMTM, PWMDT, and PWMSYNCWT) con-
trol over the waveform timing in both half cycles of the PWM
period. The magnitude of each parameter in the timing diagram
is determined by multiplying the integer value in each register
by t
how dead time is incorporated into the waveforms by moving
the switching edges away from the original values set in the
PWMCHA register.
CK
PWMSYNC
to 256 t
CK
(typically 50 ns). It may be seen in the timing diagram
, is given by:
CK
T
PWMSYNC
(corresponding to 50 ns to 12.8 µs for a CLKOUT
=
t
CK
×
CK
(
PWMSYNCWT
, and define the desired on-time
ADMC(F)341
+
) 1