ADMCF341BR Analog Devices Inc, ADMCF341BR Datasheet - Page 14

• Manufacturer Part Number: ADMCF341BR
• Description: IC DSP 3CH 12BIT MOT-CTRL 28SOIC
• Manufacturer: Analog Devices Inc
• Series: Motor Controlr
• Type: Motor Controlr

Specifications of ADMCF341BR

• Rohs Status: RoHS non-compliant
• Interface: Synchronous Serial Port (SSP)
• Clock Rate: 20MHz
• Non-volatile Memory: FLASH (12 kB), ROM (12kB)
• On-chip Ram: 2.5kB
• Voltage - I/o: 5.00V
• Voltage - Core: 5.00V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (7.5mm Width)

Each switching edge is moved by an equal amount (PWMDT
t
PWMSYNC pulse, whose width is set by the PWMSYNCWT
register, is also shown. Bit 3 of the SYSSTAT register indicates
which half cycle is active. This can be useful in double update
mode, as will be discussed later.
The resultant on-times of the PWM signals shown in Figure 7
may be written as:
The corresponding duty cycles are:
Obviously, negative values of T
because the minimum permissible value is zero, corresponding
to a 0% duty cycle. In a similar fashion, the maximum value is
T
The output signals from the timing unit for operation in double
update mode are shown in Figure 8. This illustrates a completely
general case where the switching frequency, dead time, and duty
cycle are all changed in the second half of the PWM period. Of
course, the same value for any or all of these quantities could be
used in both halves of the PWM cycle. However, it can be seen
that there is no guarantee that symmetrical PWM signals will be
produced by the timing unit in this double update mode.
Additionally, it is seen that the dead time is inserted into the PWM
signals in the same way as in single update mode.
SYSSTAT (3)
CK
ADMC(F)341
S
PWMSYNC
, corresponding to a 100% duty cycle.
) to preserve the symmetrical output patterns. The
T
Figure 7. Typical PWM Outputs of Three-Phase
Timing Unit in Single Update Mode
AL
d
AL
AH
AL
= ×
T
=
2 (
AH
d
2
T
T
AH
AL
S
PWMDT
PWMTM
= ×
=
2 (
=
T
T
PWMTM
PWMTM
AH
S
PWMCHA PWMDT
=
−
PWMCHA PWMDT
PWMCHA
PWMCHA PWMDT
AH
−
PWMCHA PWMDT
PWMTM
PWMTM
and T
−
PWMCHA
−
AL
−
are not permitted
PWMSYNCWT + 1
PWMTM
−
)
×
2
t
CK
PWMDT
)
×
t
CK
–14–
In general, the on-times of the PWM signals in double update
mode are defined by:
because for the completely general case in double update mode,
the switching period is given by:
Again, the values of T
zero and T
PWM signals similar to those illustrated in Figure 7 and Figure 8
can be produced on the BH, BL, CH, and CL outputs by
programming the PWMCHB and PWMCHC registers in a
manner identical to that described for PWMCHA.
The PWM controller does not produce any PWM outputs until
all of the PWMTM, PWMCHA, PWMCHB, and PWMCHC
registers have been written to at least once. After these registers
have been written, the counters in the three-phase timing unit
are enabled. Writing to these registers also starts the main PWM
timer. If, during initialization, the PWMTM register is written
before the PWMCHA, PWMCHB, and PWMCHC registers,
the first PWMSYNC pulse (and interrupt if enabled) will be
generated (1.5 × t
to the PWMTM register in single update mode. In double update
mode, the first PWMSYNC pulse will be generated (t
PWMTM) seconds after the initial write to the PWMTM register
in single update mode.
SYSSTAT (3)
PWMSYNC
d
d
PWMCHA
PWMCHA
AH
AL
Figure 8. Typical PWM Outputs of Three-Phase
Timing Unit in Double Update Mode
PWMTM
AH
AL
=
=
T
(
PWMCHA
PWMTM
S
T
AL
T
T
.
T
2
PWMTM
AH
AL
S
T
S
=
S
PWMDT
PWMSYNCWT
1
1
=
=
2
=
T
(
PWMDT
+
+
CK
PWMCHA
+
PWMTM
PWMTM
AH
(
PWMCHA
PWMTM
PWMTM
PWMDT
1
1
× PWMTM) seconds after the initial write
2
AH
=
+
1
−
PWMTM
+
1
PWMDT
and T
PWMCHA
PWMTM
PWMTM
1
1
+ 1
−
1
1
1
2
1
PWMDT
+
+
AL
+
2
+
PWMTM
1
PWMCHA
PWMCHA
−
PWMTM
are constrained to lie between
2
1
PWMTM
PWMCHA
PWMDT
−
1
−
2
+
PWMDT
PWMCHA
PWMTM
2
)
×
2
2
PWMTM
2
T
+
PWMSYNCWT
1
2
)
CK
1
1
PWMCHA
−
×
+
+
2
t
)
PWMDT
PWMTM
CK
2
1
2
×
2
−
t
CK
PWMDT
2
+ 1
CK
REV. B
1
2
2
2
−
×