EP3C5F256C8N Altera, EP3C5F256C8N Datasheet - Page 35

• Manufacturer Part Number: EP3C5F256C8N
• Description: IC CYCLONE III FPGA 5K 256-FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C5F256C8N

• Number Of Logic Elements/cells: 5136
• Number Of Labs/clbs: 321
• Total Ram Bits: 423936
• Number Of I /o: 182
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 256-FBGA
• No. Of Logic Blocks: 321
• Family Type: Cyclone III
• No. Of I/o's: 182
• I/o Supply Voltage: 3.3V
• Operating Frequency Max: 402MHz
• Operating Temperature Range: 0°C To +85°C
• Rohs Compliant: Yes
• For Use With: 544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2423; EP3C5F256C8N

Design and Compilation
Design Assistant
Figure 7. Design Assistant Rules
Planning for Hierarchical and Team-Based Design
© November 2008 Altera Corporation
f
The Quartus II Design Assistant analyzes the reliability of a design based on
Altera-recommended design guidelines or design rules during design compilation.
The Design Assistant checks rules related to areas such as clocks, resets, timing
closure, and non-synchronous design structure. You can select the areas you want the
Design Assistant to check and the Design Assistant will report any design violation
based on the settings you specified. The HardCopy rules are not applicable to designs
targeting Cyclone III devices.
To turn on the Design Assistant, on the Assignments menu, click Settings. Select the
design rules under Design Assistant.
checks.
For more information about the Design Assistant, refer to the
for Altera Devices and the Quartus II Design Assistant
Quartus II Handbook.
The Quartus II incremental compilation feature preserves the results and performance
of the unchanged logic in your design as you make changes elsewhere, allowing you
to perform more design iterations, achieve timing closure efficiently and reduce
compilation time when changes are made to certain partitions of the design.
In an incremental compilation flow, a large design is split into smaller partitions that
can be designed separately and independently to simplify the design process and
reduce compilation time. Good partition and floorplan design helps lower-level
design blocks meet top-level design requirements, reducing the time spent integrating
and verifying the timing of the top-level design.
Figure 7
shows the areas the Design Assistant
chapter in volume 1 of the
Design Recommendations
Page 35