EP3C5F256C8N Altera, EP3C5F256C8N Datasheet - Page 53
![IC CYCLONE III FPGA 5K 256-FBGA](/photos/6/70/67063/544-256-fbga_sml.jpg)
EP3C5F256C8N
Manufacturer Part Number
EP3C5F256C8N
Description
IC CYCLONE III FPGA 5K 256-FBGA
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
6.EP3C10M164C8N.pdf
(350 pages)
Specifications of EP3C5F256C8N
Number Of Logic Elements/cells
5136
Number Of Labs/clbs
321
Total Ram Bits
423936
Number Of I /o
182
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
256-FBGA
No. Of Logic Blocks
321
Family Type
Cyclone III
No. Of I/o's
182
I/o Supply Voltage
3.3V
Operating Frequency Max
402MHz
Operating Temperature Range
0°C To +85°C
Rohs Compliant
Yes
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-2423
EP3C5F256C8N
EP3C5F256C8N
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3C5F256C8N
Manufacturer:
ALTERA
Quantity:
853
Part Number:
EP3C5F256C8N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Verification
Figure 13. Specifying the Number of Processors
© November 2008 Altera Corporation
f
Preserving Performance
You can use the incremental compilation feature to preserve unchanged parts of your
design, thus preserving performance and allowing you to reach timing closure more
efficiently. For guidelines and references, refer to
Team-Based Design” on page
Reducing Compilation Time
You can speed up design iteration time by an average of 60% when making changes to
the design with the incremental compilation feature.
For guidelines and references, refer to the
Design” on page
The Quartus II software can run some algorithms in parallel to take advantage of
multiple processors and reduce compilation time when more than one processor is
available to compile the design. To set the number of processors available for a
Quartus II compilation, specify the Maximum processors allows for parallel
compilation on the Compilation Process Settings page of the Settings dialog box, as
in
parallel compilation.
Figure
13. The default value for the number of processors is 1, which disables
35.
35.
“Planning for Hierarchical and Team-Based
“Planning for Hierarchical and
Page 53