EP1C3T144C7 Altera, EP1C3T144C7 Datasheet

IC CYCLONE FPGA 2910 LE 144-TQFP

EP1C3T144C7

Manufacturer Part Number
EP1C3T144C7
Description
IC CYCLONE FPGA 2910 LE 144-TQFP
Manufacturer
Altera
Series
Cyclone®r
Datasheet

Specifications of EP1C3T144C7

Number Of Logic Elements/cells
2910
Number Of Labs/clbs
291
Total Ram Bits
59904
Number Of I /o
104
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
144-TQFP, 144-VQFP
Family Name
Cyclone®
Number Of Logic Blocks/elements
2910
# I/os (max)
104
Frequency (max)
320.1MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
2910
Ram Bits
59904
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
144
Package Type
TQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-1051

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Revision History
Altera Corporation
This section provides designers with the data sheet specifications for
Cyclone
architecture, configuration and JTAG boundary-scan testing information,
DC operating conditions, AC timing parameters, a reference to power
consumption, and ordering information for Cyclone devices.
This section contains the following chapters:
Refer to each chapter for its own specific revision history. For information
on when each chapter was updated, refer to the Chapter Revision Dates
section, which appears in the complete handbook.
Chapter 1. Introduction
Chapter 2. Cyclone Architecture
Chapter 3. Configuration and Testing
Chapter 4. DC and Switching Characteristics
Chapter 5. Reference and Ordering Information
®
devices. The chapters contain feature definitions of the internal
Section I. Cyclone FPGA
Family Data Sheet
Preliminary
Section I–1

Related parts for EP1C3T144C7

EP1C3T144C7 Summary of contents

Page 1

... Revision History Refer to each chapter for its own specific revision history. For information on when each chapter was updated, refer to the Chapter Revision Dates section, which appears in the complete handbook. Altera Corporation Section I. Cyclone FPGA Family Data Sheet ® devices. The chapters contain feature definitions of the internal Chapter 1 ...

Page 2

... Revision History Section I–2 Preliminary Cyclone Device Handbook, Volume 1 Altera Corporation ...

Page 3

... Cyclone devices support various I/O standards, including LVDS at data rates up to 640 megabits per second (Mbps), and 66- and 33-MHz, 64- and 32-bit peripheral component interconnect (PCI), for interfacing with and supporting ASSP and ASIC devices. Altera also offers new low-cost serial configuration devices to configure Cyclone devices. ...

Page 4

... EP1C6 EP1C12 EP1C20 92,160 239,616 294,912 185 249 301 through 1–3). 324-Pin 400-Pin FineLine BGA FineLine BGA — — — — 249 301 — — 249 — — 233 301 ® II Altera Corporation May 2008 ...

Page 5

... Added 64-bit PCI support information. v1.2 September ● Updated LVDS data rates to 640 Mbps from 311 Mbps. 2003 v1.1 ● Updated RSDS feature information. May 2003 v1.0 Added document to Cyclone Device Handbook. Altera Corporation May 2008 256-Pin 144-Pin 240-Pin FineLine TQFP PQFP BGA 0.5 ...

Page 6

... Cyclone Device Handbook, Volume 1 1–4 Preliminary Altera Corporation May 2008 ...

Page 7

... The global clock lines can also be used for control signals. Cyclone PLLs provide general-purpose clocking with clock multiplication and phase shifting as well as external outputs for high-speed differential I/O support. Figure 2–1 Altera Corporation May 2008 2. Cyclone Architecture ® devices contain a two-dimensional row- and column-based shows a diagram of the Cyclone EP1C12 device. 2– ...

Page 8

... The number of M4K RAM blocks, PLLs, rows, and columns vary per device. Table 2–1. Cyclone Device Resources Device Columns EP1C3 1 EP1C4 1 EP1C6 1 EP1C12 2 EP1C20 2 2–2 Preliminary EP1C12 Device Table 2–1 lists the resources available in each Cyclone device. M4K RAM PLLs Blocks LAB Columns LAB Rows Altera Corporation May 2008 ...

Page 9

... LAB's local interconnect through the direct link connection. The direct link connection feature minimizes the use of row and column interconnects, providing higher Altera Corporation May 2008 Figure 2–2 details the Cyclone LAB. ...

Page 10

... The asynchronous load acts as a preset when the asynchronous load data input is tied high. 2–4 Preliminary Local Figure 2–3 shows the direct link Direct link interconnect from right LAB, M4K memory block, PLL, or IOE output Direct link interconnect to right LAB Altera Corporation May 2008 ...

Page 11

... LE also supports dynamic single bit addition or subtraction mode selectable by a LAB-wide control signal. Each LE drives all types of interconnects: local, row, column, LUT chain, register chain, and direct link interconnects. See Altera Corporation May 2008 shows the LAB control signal generation circuit. labclkena2 ...

Page 12

... Carry-Out0 Carry-Out1 LAB Carry-Out Programmable Packed Register Register Select LUT chain routing to next LE Row, column, PRN/ALD and direct link D Q routing ADATA ENA CLRN Row, column, and direct link routing Local Routing Register chain Register output Feedback Altera Corporation May 2008 ...

Page 13

... LE, the LAB carry-in from the previous carry-chain LAB, and the register chain connection⎯ are directed to different destinations to implement the desired logic function. LAB-wide signals provide clock, asynchronous clear, asynchronous Altera Corporation May 2008 for more information on LUT chain and Normal mode ...

Page 14

... Wide) ena (LAB Wide) aclr (LAB Wide) Figure 2–6). The aload (LAB Wide) ALD/PRE ADATA Row, column, and Q direct link routing D Row, column, and ENA direct link routing CLRN Local routing LUT chain connection Register chain output Altera Corporation May 2008 ...

Page 15

... LABs. The addnsub LAB-wide signal controls whether the LE acts as an adder or subtractor. Altera Corporation May 2008 2–7, the LAB carry-in signal selects either the carry-in0 or data1 + data2 + carry-in0 ...

Page 16

... Wide) ena (LAB Wide) aclr (LAB Wide) Register Feedback Carry-Out1 aload (LAB Wide) ALD/PRE ADATA Row, column, and Q direct link routing D Row, column, and ENA direct link routing CLRN Local routing LUT chain connection Register chain output Altera Corporation May 2008 ...

Page 17

... A7 LE7 B7 Sum8 A8 LE8 B8 Sum9 A9 LE9 B9 Sum10 A10 LE10 B10 LAB Carry-Out Altera Corporation May 2008 shows the carry-select circuitry in a LAB for a 10-bit full adder. LAB Carry-In Carry-In0 Carry-In1 data1 data2 Carry-Out0 Logic Elements LUT Sum LUT LUT LUT Carry-Out1 2–11 ...

Page 18

... The MultiTrack interconnect consists of row and column interconnects that span fixed distances. A routing structure with fixed length resources for all devices allows predictable and repeatable performance when 2–12 Preliminary TM technology. The MultiTrack interconnect Altera Corporation May 2008 ...

Page 19

... R4 interconnects can drive other R4 interconnects to extend the range of LABs they can drive. R4 interconnects can also drive C4 interconnects for connections from one row to another. Altera Corporation May 2008 Direct link interconnects between LABs and adjacent blocks R4 interconnects traversing four blocks to the right or left Figure 2– ...

Page 20

... LAB's R4 Interconnect LAB Primary LAB Neighbor LAB (2) Neighbor LUT chain interconnects within a LAB Register chain interconnects within a LAB C4 interconnects traversing a distance of four blocks and down direction Figure 2–10 shows the LUT chain and register chain R4 Interconnect Driving Right Altera Corporation May 2008 ...

Page 21

... IOEs. For LAB interconnection, a primary LAB or its LAB neighbor can drive a given C4 interconnect. C4 interconnects can drive each other to extend their range as well as drive row interconnects for column-to-column connections. Altera Corporation May 2008 Local Interconnect Routing Among LEs in the LAB ...

Page 22

... Adjacent LAB can drive onto neighboring LAB's C4 interconnect Note to Figure 2–11: (1) Each C4 interconnect can drive either up or down four rows. 2–16 Preliminary Note (1) Local Interconnect C4 Interconnect Drives Local and R4 Interconnects Up to Four Rows C4 Interconnect Driving Up LAB C4 Interconnect Driving Down Altera Corporation May 2008 ...

Page 23

... C4 Interconnect — — M4K RAM Block — — PLL — — Column IOE — — Row IOE — — Altera Corporation May 2008 shows the Cyclone device's routing scheme. Destination v — — — — v — — — — v — — — ...

Page 24

... Violating the setup or hold time on the address registers could corrupt the memory contents. This applies to both read and write operations. A data [ ] A address [ ] A wren A clock A clocken aclr A Table 1–1 on Figure 2–12 shows true B data [ ] B address [ ] B wren B clock B clocken aclr B Altera Corporation May 2008 ...

Page 25

... In contrast, a circuit using asynchronous RAM must generate the RAM wren signal while ensuring its data and address signals meet setup and hold time specifications relative to the wren Altera Corporation May 2008 Simple Dual-Port Memory data[ ] ...

Page 26

... The size × m × n shift register is determined by the input data width (w), the length of the taps (m), and the number of taps (n). The size × m × n shift register must be less than or equal to the maximum number of memory bits in the M4K block (4,608 bits). The total number of shift 2–20 Preliminary Altera Corporation May 2008 ...

Page 27

... The memory address depths and output widths can be configured as 4,096 × 1, 2,048 × 2, 1,024 × 4, 512 × 8 (or 512 × 9 bits), 256 × 16 (or 256 × 18 bits), and 128 × 32 (or 128 × 36 bits). The 128 × 32- or 36-bit configuration Altera Corporation May 2008 Embedded Memory Figure 2– ...

Page 28

... Altera Corporation May 2008 ...

Page 29

... M4K block are possible from the left adjacent LABs and another 10 possible from the right adjacent LAB. M4K block outputs can also connect to left and right LABs through 10 direct link interconnects each. array interface. Altera Corporation May 2008 Table 2–5 summarizes the byte selection. byteena[3..0] datain × ...

Page 30

... M4K RAM Block Byte enable Control Signals Clocks address datain LAB Row Clocks Local Interconnect Local Interconnect Local Interconnect Local Interconnect clock_b Local Interconnect clocken_b R4 Interconnects Direct link interconnect to adjacent LAB Direct link interconnect from adjacent LAB 6 Altera Corporation May 2008 ...

Page 31

... The other clock controls the block's data output registers. Each memory block port also supports independent clock enables and asynchronous clear signals for input and output registers. clock mode. Altera Corporation May 2008 Figure 2–17 Notes (1), (2) ...

Page 32

... Byte Enable A Byte Enable B Address A Address B Write/Read Write/Read Write Enable Enable Pulse Data Out Data Out ENA ENA (1), ( ENA Q D ENA Q D ENA Write Q D Pulse ENA Generator Altera Corporation May 2008 data [ ] B byteena [ ] B address [ ] B wren B clken B clock B ...

Page 33

... All registers shown except the rden register have asynchronous clear ports. (2) Violating the setup or hold time on the address registers could corrupt the memory contents. This applies to both read and write operations. Altera Corporation May 2008 Notes Memory Block 256 ´ ...

Page 34

... D Q Data In 2,048 × 2 ENA 4,096 × 1 Data Out D Q Read Address ENA Write Address D Q ENA Byte Enable D Q ENA Read Enable D Q ENA Write D Q Write Enable Pulse ENA Generator (1), (2) To MultiTrack Interconnect D Q ENA Altera Corporation May 2008 ...

Page 35

... There are four dedicated clock pins (CLK[3..0], two pins on the left side and two pins on the right side) that drive the global clock network, as shown in (DPCLK[7..0]) pins can also drive the global clock network. Altera Corporation May 2008 Global Clock Network and Phase-Locked Loops Note (1) ...

Page 36

... The EP1C3 device in the 100-pin TQFP package does not have dedicated clock pins CLK1 and CLK3. (3) 2–30 Preliminary Figure 2–22 shows the various sources that drive the global clock Note (1) DPCLK2 DPCLK3 8 From logic From logic array array DPCLK7 DPCLK6 Global Clock Network DPCLK4 CLK2 PLL2 CLK3 (3) (2) 2 DPCLK5 Altera Corporation May 2008 ...

Page 37

... IOE clocks have row and column block regions. Six of the eight global clock resources feed to these row and column regions. the I/O clock regions. Altera Corporation May 2008 Global Clock Network and Phase-Locked Loops 2–23. Another multiplexer at the LAB level selects two of the six ...

Page 38

... Preliminary Column I/O Clock Region IO_CLK[5..0] LAB Row Clocks labclk[5..0] LAB Row Clocks labclk[5..0] Global Clock Network 8 LAB Row Clocks labclk[5..0] Column I/O Clock Region IO_CLK[5..0] I/O Clock Regions 6 6 Row I/O Regions 6 I/O Clock Regions Altera Corporation May 2008 ...

Page 39

... LVDSCLK1p and the CLK1 pin’s secondary function is LVDSCLK1n. For PLL 2, the CLK2 pin’s secondary function is LVDSCLK2p and the CLK3 pin’s secondary function is LVDSCLK2n. (3) PFD: phase frequency detector. Altera Corporation May 2008 Global Clock Network and Phase-Locked Loops shows the PLL features in Cyclone devices. ...

Page 40

... CLK2 g1 PLL2 CLK3 (2) e PLL2_OUT (3), (4) GCLK4 GCLK5 GCLK6 GCLK7 — — — — — — — — — — — — — — — — — — — — — — — — Altera Corporation May 2008 ...

Page 41

... E divider for external clock output, both ranging from 1 to 32. The Quartus II software automatically chooses the appropriate scaling factors according to the input frequency, multiplication, and division values entered. Altera Corporation May 2008 Global Clock Network and Phase-Locked Loops GCLK1 ...

Page 42

... The EP1C3 device in the 100-pin TQFP package 2–36 Preliminary Figure 2–25. shows the I/O standards supported by PLL input and output I/O Standard CLK Input 2–54. Table 2–8. EXTCLK Output — “LVDS I/O Pins” on and ground voltage CC Altera Corporation May 2008 ...

Page 43

... Therefore, you may need to gate the lock signal for use as a system-control signal. For correct operation of the lock circuit below – Altera Corporation May 2008 Global Clock Network and Phase-Locked Loops Zero delay buffer mode⎯ The external clock output pin is phase- aligned with the clock input pin for zero delay. Normal mode⎯ ...

Page 44

... You can either use their own control signal or gated locked status signals to trigger the pfdena signal. f For more information about Cyclone PLLs, refer to Devices 2–38 Preliminary chapter in the Cyclone Device Handbook. Using PLLs in Cyclone Altera Corporation May 2008 ...

Page 45

... The Quartus II software automatically duplicates a single OE register that controls multiple output or bidirectional pins. IOEs can be used as input, output, or bidirectional pins. Altera Corporation May 2008 Differential and single-ended I/O standards 3.3-V, 64- and 32-bit, 66- and 33-MHz PCI compliance ...

Page 46

... Output Register Output D Combinatorial input (1) Input Input Register D Figure 2–27: There are two paths available for combinatorial inputs to the logic array. Each path contains a unique programmable delay chain Figure 2–28 shows how a row Figure 2–29 shows how a column Altera Corporation May 2008 ...

Page 47

... Each of the three IOEs in the row I/O block can have one io_datain input (combinatorial or registered) and one (2) comb_io_datain (combinatorial) input. Altera Corporation May 2008 C4 Interconnects I/O Block Local Interconnect 21 io_datain[2 ...

Page 48

... Each of the three IOEs in the column I/O block can have one io_datain input (combinatorial or registered) and (2) one comb_io_datain (combinatorial) input. 2–42 Preliminary Column I/O Block IO_datain[2:0] & 21 comb_io_datain[2..0] (2) LAB C4 Interconnects Column I/O Block Contains up to Three IOEs io_clk[5..0] LAB Altera Corporation May 2008 ...

Page 49

... Array io_caclr io_cclk io_dataout Each IOE contains its own control signal selection for the following control signals: oe, ce_in, ce_out, aclr/preset, sclr/preset, clk_in, and clk_out. selection. Altera Corporation May 2008 illustrates the signal paths through the I/O block. To Other IOEs oe ce_in ce_out ...

Page 50

... The OE and output register share the same clock source and the same clock enable source from the local interconnect in the associated LAB, dedicated I/O clocks, or the column and row interconnects. Figure 2–32 2–44 Preliminary ce_out clk_out clk_in ce_in shows the IOE in bidirectional configuration. sclr/preset aclr/preset oe Altera Corporation May 2008 ...

Page 51

... Programmable delays decrease input-pin-to-logic-array and IOE input register delays. The Quartus II Compiler can program these delays Altera Corporation May 2008 OE Register PRN ...

Page 52

... SSTL-2 V 2–46 Preliminary Table 2–9 shows the programmable delays for Cyclone devices. Programmable Delays Decrease input delay to internal cells Decrease input delay to input registers Increase delay to output pin level is 2.5 V. Additionally, the configuration CCIO Quartus II Logic Option Altera Corporation May 2008 ...

Page 53

... Each DQ group consists of one DQS pin, eight DQ pins, and one DM pin. Table 2–10 Table 2–10. DQ Pin Groups (Part Device EP1C3 EP1C4 Altera Corporation May 2008 Note (1) DQ Pins DQS Pin shows the number of DQ pin groups per device. Number of × Package ...

Page 54

... Resynchronize the incoming data to the logic array clock using successive LE registers or FIFO buffers LE registers must be placed in the LAB adjacent to the DQ I/O pin column it is fed by illustrates DDR SDRAM and FCRAM interfacing from the Number of × Total DQ Pin Pin Groups Count Altera Corporation May 2008 ...

Page 55

... I/O standards. The LVTTL and LVCMOS standards have several levels of drive strength that the designer can control. SSTL-3 class I and II, and SSTL-2 class I and II support a minimum setting, the lowest drive strength that guarantees the I Altera Corporation May 2008 DQS OE ...

Page 56

... SSTL-3 class I and II, SSTL-2 class I and II, and 3.3-V PCI I/O Standards do not support programmable drive strength. This is the default current strength setting in the Quartus II software. Table 2–11 shows the Note ( Current Strength Setting (mA 24( 12( 16( 12( 8(2) Altera Corporation May 2008 ...

Page 57

... I/O pin, the pull-up resistor (typically 25 kΩ) holds the output to the V CCIO optional programmable pull-up resistor. Altera Corporation May 2008 gives the specific sustaining current for each voltage level driven through this resistor and overdrive current level of the output pin's bank. Dedicated clock pins do not have the ...

Page 58

... Output Supply Termination Voltage (V ) (V) CCIO Voltage (V ) (V) TT 3.3 N/A 2.5 N/A 1.8 N/A 1.5 N/A 3.3 N/A 2.5 N/A 2.5 N/A 2.5 1.25 3.3 1.5 2.5 1.25 Figure 2–35. I/O Table 2–12. I/O Table 2–12 except the Altera Corporation May 2008 ...

Page 59

... I/O voltages. Each bank also has dual-purpose VREF pins to support any one of the voltage-referenced standards (e.g., SSTL-3) independently I/O bank does not use voltage-referenced standards, the V Altera Corporation May 2008 Notes (1), (2) ...

Page 60

... Table 2–13: EP1C3 devices in the 100-pin TQFP package do not support the LVDS I/O standard. ). CCIO for CCIO is 3.3-V, a bank can CCIO Number of LVDS Channels (1) 34 103 129 103 95 129 pins for CC ), and four sets for I/O CCINT Altera Corporation May 2008 ...

Page 61

... Signals can be driven into Cyclone devices before and during power up without damaging the device. In addition, Cyclone devices do not drive out during power up. Once operating conditions are reached and the device is configured, Cyclone devices operate as specified by the user. Altera Corporation May 2008 pins must always be connected to a 1.5-V power CCINT level is 1 ...

Page 62

... Preliminary Using PLLs in Cyclone Devices chapter in the Cyclone Device Handbook shows the revision history for this chapter. Changes Made “Referenced 2–17, 2–18, 2–19, 2–20, 2–21, and 2–32. Summary of Changes — — — — — — — Altera Corporation May 2008 ...

Page 63

... PRELOAD 00 0000 0101 / EXTEST (1) 00 0000 0000 BYPASS 11 1111 1111 Altera Corporation May 2008 3. Configuration and Testing ® devices provide JTAG BST circuitry that complies with the ® II software or hardware using either Jam Files (.jam) or Jam CCIO selects whether the JTAG inputs are 1.5-V, 1.8-V, 2.5-V, or CCIO ® ...

Page 64

... Stops configuration if executed during configuration. CONFIG_IO Once issued, the instruction will hold nSTATUS to reset the configuration device. device is reconfigured. Monitors internal device operation with the SignalTap II embedded logic analyzer. download cable, or when nSTATUS low is held low until the Altera Corporation May 2008 ...

Page 65

... EP1C12 0000 EP1C20 Notes to Table 3–3: (1) The most significant bit (MSB the left. The IDCODE’s least significant bit (LSB) is always 1. (2) Altera Corporation May 2008 IEEE Std. 1149.1 (JTAG) Boundary Scan Support Device EP1C3 EP1C4 EP1C6 EP1C12 EP1C20 IDCODE (32 bits) ...

Page 66

... Update register clock to output Update register high impedance to valid output Update register valid output to high impedance t t JPH JPSU t JPXZ t JSXZ Min Max Unit 100 — 50 — 50 — 20 — 45 — — 25 — 25 — — 45 — — 35 — 35 — 35 Altera Corporation May 2008 ...

Page 67

... All of these devices have the same JTAG controller. If any of the Cyclone devices are in the 9th or after they will fail configuration. This does not affect the SignalTap analyzer. AN 39: IEEE Std. 1149.1 (JTAG) Boundary-Scan Testing in Altera Devices Jam Programming & Test Language Specification SignalTap II Embedded Logic Analyzer ® ...

Page 68

... Cyclone device at system power-up. 3–6 Preliminary of the bank where the pins reside. The bank CCIO selects whether the configuration inputs are 1.5-V, 1.8-V, 2.5-V, or Table before CCIO 3–5), chosen on the basis of the Altera Corporation May 2008 ...

Page 69

... MasterBlaster or ByteBlasterMV download cable, or serial data source MasterBlaster or ByteBlasterMV download cable or a microprocessor with a Jam or JBC file AN 39: IEEE Std. 1149.1 (JTAG) Boundary-Scan Testing in Altera Devices Jam Programming & Test Language Specification shows the revision history for this chapter. Changes Made “ ...

Page 70

... Cyclone Device Handbook, Volume 1 3–8 Preliminary Altera Corporation May 2008 ...

Page 71

... Supply voltage for output buffers, 2.5-V operation Supply voltage for output buffers, 1.8-V operation Supply voltage for output buffers, 1.5-V operation V Input voltage I Altera Corporation May 2008 4. DC and Switching ® devices are offered in both commercial, industrial, and through 4–16 provide information on absolute maximum Notes ...

Page 72

... Maximum Unit V V CCIO ° ° C 100 ° C 125 μA — 10 μA — — — — — — kΩ kΩ 65 100 kΩ 100 150 kΩ kΩ Maximum Unit 3.0 3.6 V 1.7 4.1 V 0.7 V 2.4 — V — 0.45 V Altera Corporation May 2008 ...

Page 73

... Table 4–7. 1.8-V I/O Specifications Symbol Parameter V Output supply voltage CCIO V High-level input voltage Low-level input voltage IL V High-level output voltage OH V Low-level output voltage OL Altera Corporation May 2008 Conditions Minimum — 3.0 — 1.7 — –0 3.0, V – 0.2 CCIO CCIO I = –0.1 mA ...

Page 74

... CCIO — V CCIO 0.25 × — CCIO Typical Maximum Unit 2.5 2.625 V — 550 mV — 1.25 1.375 V — — 100 mV — 2.4 V Ω 100 110 Typical Maximum Unit 3.3 3.6 V — CCIO 0.5 0.3 × — CCIO Altera Corporation May 2008 ...

Page 75

... IL V High-level output voltage OH V Low-level output voltage OL Table 4–13. SSTL-3 Class I Specifications (Part Symbol Parameter V Output supply voltage CCIO V Termination voltage TT Altera Corporation May 2008 Conditions Minimum = –500 μA 0.9 × I OUT V CCIO = 1,500 μA I — OUT Conditions Minimum Typical — ...

Page 76

... V + 0.3 CCIO — V – 0 — — — V – 0.8 TT 2.5 V 3.3 V Min Max Min Max 50 — 70 — –50 — –70 — — 300 — 500 — –300 — –500 Altera Corporation May 2008 Unit μA μA μA μA ...

Page 77

... Notes to Tables 4–1 through 4–16: (1) Refer to the Operating Requirements for Altera Devices Data (2) Conditions beyond those listed in operation at the absolute maximum ratings for extended periods of time may have adverse affects on the device. (3) Minimum DC input is –0.5 V. During transitions, the inputs may undershoot to –2 overshoot to 4.6 V for input currents less than 100 mA and periods shorter than 20 ns ...

Page 78

... Cyclone Device Handbook, Volume 1 Power Designers can use the Altera web Early Power Estimator to estimate the device power. Consumption Cyclone devices require a certain amount of power-up current to successfully power up because of the nature of the leading-edge process on which they are fabricated. current required to power up a Cyclone device. ...

Page 79

... Typically, the user-mode current during device operation is lower than the power-up current in Cyclone Power Calculator, available on the Altera web site, to estimate the user-mode I regulators based on the higher value. Timing Model The DirectDrive technology and MultiTrack interconnect ensure predictable performance, accurate simulation, and accurate timing analysis across all Cyclone device densities and speed grades ...

Page 80

... Speed Grade Units Max Min Typ Max 320 — — 275 Performance -6 Speed -7 Speed -8 Speed Grade Grade Grade (MHz) (MHz) (MHz) — 405.00 320.00 275.00 — 317.36 284.98 260.15 — 405.00 320.00 275.00 — 208.99 181.98 160.75 Altera Corporation May 2008 MHz ...

Page 81

... Cyclone device internal timing microparameters for LEs, IOEs, M4K memory structures, and MultiTrack interconnects. Table 4–21. LE Internal Timing Microparameter Descriptions LUT t CLR t PRE t CLKHL Altera Corporation May 2008 Resources Used M4K M4K Mode LEs Memory Memory Bits Blocks — 4,608 — 4,608 — 4,608 — ...

Page 82

... B port data hold time after clock B port address setup time before clock B port address hold time after clock Clock-to-output delay when using output registers Clock-to-output delay without output registers Minimum clock high or low time Minimum clear pulse width Parameter Parameter Altera Corporation May 2008 ...

Page 83

... Altera Corporation May 2008 Symbol Delay for an R4 line with average loading; covers a distance of four LAB columns Delay for an C4 line with average loading; covers a distance of four LAB rows Local interconnect delay shows the memory waveforms for the M4K timing parameters Table 4– ...

Page 84

... Altera Corporation May 2008 Unit Unit ...

Page 85

... M4KCLR Table 4–28. Routing Delay Internal Timing Microparameters LOCAL External Timing Parameters External timing parameters are specified by device density and speed grade. timing. All registers are within the IOE. Altera Corporation May 2008 -6 Symbol Min Max — 4,379 — 2,910 72 — ...

Page 86

... Input Register PRN D Q CLRN through 4–44. shows the external I/O timing parameters when using global Parameter CLK pin CLK pin CLK pin INSU t INH t OUTCO Bidirectional Pin Notes (1), (2) (Part Conditions — — LOAD — — Altera Corporation May 2008 ...

Page 87

... Table 4–31. EP1C3 Row Pin Global Clock External I/O Timing Parameters Symbol Altera Corporation May 2008 Notes Parameter through 4–31 show the external timing parameters on column -6 Speed Grade -7 Speed Grade Min Max Min 3.085 — 3.547 0.000 — 0.000 2.000 4.073 2 ...

Page 88

... Tables 4–32 and 4–33: Contact Altera Applications for EP1C4 device timing parameters. -8 Speed Grade Unit Max Min Max — 3.210 — ns — 0.000 — ns 4.526 2.000 5.119 ns — ...

Page 89

... EP1C12 devices. Table 4–36. EP1C12 Column Pin Global Clock External I/O Timing Parameters (Part Symbol Altera Corporation May 2008 through 4–35 show the external timing parameters on column -6 Speed Grade -7 Speed Grade Min Max Min Max 2.691 — ...

Page 90

... Speed Grade Unit Min Max 3.404 — ns 0.000 — ns 2.000 4.774 ns 2.206 — ns 0.000 — ns 0.500 1.998 ns -8 Speed Grade Unit Min Max 3.140 — ns 0.000 — ns 2.000 4.843 ns 1.840 — ns 0.000 — ns 0.500 2.169 ns Altera Corporation May 2008 ...

Page 91

... LVTTL — 2.5-V LVTTL — 1.8-V LVTTL — 1.5-V LVTTL — SSTL-3 class I — SSTL-3 class II — SSTL-2 class I — Altera Corporation May 2008 -6 Speed Grade -7 Speed Grade Min Max Min 2.417 — 2.779 0.000 — 0.000 2.000 3.724 2.000 — ...

Page 92

... Speed Grade Unit Min Max — — –636 ps — –1,112 ps — –1,291 ps — — –452 ps — –1,116 ps — –1,065 ps — –1,291 ps Altera Corporation May 2008 ...

Page 93

... LVTTL 4 mA — — — — — 2.5-V LVTTL 2 mA — — — — Altera Corporation May 2008 -7 Speed Grade Max Min Max 329 — 378 –661 — –761 –655 — –754 –795 — –915 4 — 4 –208 — ...

Page 94

... Speed Grade Unit Min Max — 2,340 ps — 1,704 ps — 1,228 ps — 1,049 ps — 2,380 ps — 1,928 ps — 1,264 ps — 1,315 ps — 1,089 ps — 3,570 ps — 2,283 ps — 2,291 ps — 2,109 ps — 7,157 ps — 5,485 ps — 5,209 ps Altera Corporation May 2008 ...

Page 95

... LVTTL 2 mA — — — 1.5-V LVTTL 2 mA — — — 3.3-V PCI — Altera Corporation May 2008 -7 Speed Grade Max Min Max 6,789 — 7,807 5,109 — 5,875 4,793 — 5,511 1,390 — 1,598 989 — ...

Page 96

... Speed Grade Unit Min Max — 1,807 ps — 1,285 ps — 2,554 ps — 2,199 ps — 1,042 ps -8 Speed Grade Unit Min Max — 201 ps — 2,875 ps — 3,430 ps — 3,974 ps — 201 ps — — 3,974 ps — — 717 ps Altera Corporation May 2008 ...

Page 97

... Cyclone devices. Table 4–48. Cyclone Maximum Input Clock Rate for Column Pins LVTTL 2.5 V 1.8 V 1.5 V LVCMOS SSTL-3 class I SSTL-3 class II SSTL-2 class I SSTL-2 class II LVDS Altera Corporation May 2008 -6 Speed Grade -7 Speed Grade Min Max Min — 154 — — 2,212 — ...

Page 98

... MHz -7 Speed -8 Speed Unit Grade Grade 304 304 MHz 220 220 MHz 213 213 MHz 166 166 MHz 304 304 MHz 100 100 MHz 100 100 MHz 134 134 MHz 134 134 MHz 320 275 MHz Altera Corporation May 2008 ...

Page 99

... Input clock period jitter IN f (external PLL PLL output frequency OUT_EXT (-6 speed grade) clock output) PLL output frequency (-7 speed grade) PLL output frequency (-8 speed grade) Altera Corporation May 2008 -6 Speed I/O Standard Grade 296 381 286 219 367 169 160 160 ...

Page 100

... Preliminary Parameter Min 15.625 15.625 15.625 45.00 — 10.00 500. smaller than 100 MHz, the jitter OUT Max Unit 405 MHz 320 MHz 275 MHz 55 % ±300 (2) ps μs 100 1,000 MHz — integer bank, how many CCIO Altera Corporation May 2008 ...

Page 101

... Tables 4-30 through 4-51. ● Updated PLL specifications in Table 4-52. Altera Corporation May 2008 Cyclone Architecture chapter in the Cyclone Device Handbook Operating Requirements for Altera Devices Data Sheet shows the revision history for this chapter. Changes Made “Referenced Document” . details in Table 4–1 CCA ...

Page 102

... Cyclone Device Handbook, Volume 1 July 2003 Updated timing information. Timing finalized for EP1C6 and v1.1 EP1C20 devices. Updated performance information. Added PLL Timing section. May 2003 Added document to Cyclone Device Handbook. v1.0 4–32 Preliminary — — Altera Corporation May 2008 ...

Page 103

... Linux Red Hat v7.1 and HP-UX operating systems. It also supports seamless integration with industry-leading EDA tools through the NativeLink Device Pin-Outs Device pin-outs for Cyclone devices are available on the Altera website (www.altera.com) and in the Cyclone Device Handbook. Ordering Figure 5–1 information about a specific package, refer to the ...

Page 104

... Optional Suffix Indicates specific device options or shipment method. ES: Engineering sample Speed Grade with 6 being the fastest Operating Temperature ˚ ˚ C: Commercial temperature ( ˚ ˚ I: Industrial temperature ( 100 C) J chapter in the Cyclone Device Summary of Changes — — — Altera Corporation May 2008 ...

Page 105

... February 2005 Updated Figure 5-1. v1.1 May 2003 Added document to Cyclone Device Handbook. v1.0 Altera Corporation May 2008 Document Revision History — — 5–3 Preliminary ...

Page 106

... Cyclone Device Handbook, Volume 1 5–4 Preliminary Altera Corporation May 2008 ...

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