EP1C3T144C7 Altera, EP1C3T144C7 Datasheet - Page 3

• Manufacturer Part Number: EP1C3T144C7
• Description: IC CYCLONE FPGA 2910 LE 144-TQFP
• Manufacturer: Altera
• Series: Cyclone®r

Specifications of EP1C3T144C7

• Number Of Logic Elements/cells: 2910
• Number Of Labs/clbs: 291
• Total Ram Bits: 59904
• Number Of I /o: 104
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 144-TQFP, 144-VQFP
• Family Name: Cyclone®
• Number Of Logic Blocks/elements: 2910
• # I/os (max): 104
• Frequency (max): 320.1MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 2910
• Ram Bits: 59904
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: TQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 544-1051

Introduction
Features
Altera Corporation
May 2008
LEs
M4K RAM blocks (128 × 36 bits)
C51001-1.5
Table 1–1. Cyclone Device Features (Part 1 of 2)
Feature
The Cyclone
0.13-μm, all-layer copper SRAM process, with densities up to
20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like
phase-locked loops (PLLs) for clocking and a dedicated double data rate
(DDR) interface to meet DDR SDRAM and fast cycle RAM (FCRAM)
memory requirements, Cyclone devices are a cost-effective solution for
data-path applications. Cyclone devices support various I/O standards,
including LVDS at data rates up to 640 megabits per second (Mbps), and
66- and 33-MHz, 64- and 32-bit peripheral component interconnect (PCI),
for interfacing with and supporting ASSP and ASIC devices. Altera also
offers new low-cost serial configuration devices to configure Cyclone
devices.
The Cyclone device family offers the following features:
■
■
■
■
■
■
■
■
■
■
■
■
2,910 to 20,060 LEs, see
Up to 294,912 RAM bits (36,864 bytes)
Supports configuration through low-cost serial configuration device
Support for LVTTL, LVCMOS, SSTL-2, and SSTL-3 I/O standards
Support for 66- and 33-MHz, 64- and 32-bit PCI standard
High-speed (640 Mbps) LVDS I/O support
Low-speed (311 Mbps) LVDS I/O support
311-Mbps RSDS I/O support
Up to two PLLs per device provide clock multiplication and phase
shifting
Up to eight global clock lines with six clock resources available per
logic array block (LAB) row
Support for external memory, including DDR SDRAM (133 MHz),
FCRAM, and single data rate (SDR) SDRAM
Support for multiple intellectual property (IP) cores, including
Altera
Program (AMPP
EP1C3
2,910
13
®
MegaCore
®
field programmable gate array family is based on a 1.5-V,
SM
EP1C4
4,000
®
) megafunctions.
17
functions and Altera Megafunctions Partners
Table 1–1
EP1C6
5,980
20
1. Introduction
EP1C12
12,060
52
Preliminary
EP1C20
20,060
64
1–1