EP2C5F256C8 Altera, EP2C5F256C8 Datasheet - Page 27

• Manufacturer Part Number: EP2C5F256C8
• Description: IC CYCLONE II FPGA 5K 256-FBGA
• Manufacturer: Altera
• Series: Cyclone® IIr

Specifications of EP2C5F256C8

• Number Of Logic Elements/cells: 4608
• Number Of Labs/clbs: 288
• Total Ram Bits: 119808
• Number Of I /o: 158
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 256-FBGA
• Family Name: Cyclone® II
• Number Of Logic Blocks/elements: 4608
• # I/os (max): 158
• Frequency (max): 402.58MHz
• Process Technology: 90nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 4608
• Ram Bits: 119808
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: FBGA
• No. Of Macrocells: 4608
• Family Type: Cyclone II
• No. Of I/o's: 158
• Clock Management: PLL
• I/o Supply Voltage: 3.6V
• Operating Frequency Max: 320MHz
• Rohs Compliant: No
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 544-1446

Altera Corporation
February 2007
Register
Chain
Local
Interconnect
Direct Link
Interconnect
R4
Interconnect
R24
Interconnect
C4
Interconnect
C16
Interconnect
Table 2–1. Cyclone II Device Routing Scheme (Part 1 of 2)
Source
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C16 column interconnects span a length of 16 LABs and provide the
fastest resource for long column connections between LABs, M4K
memory blocks, embedded multipliers, and IOEs. C16 column
interconnects drive to other row and column interconnects at every
fourth LAB. C16 column interconnects drive LAB local interconnects via
C4 and R4 interconnects and do not drive LAB local interconnects
directly. C16 interconnects can drive R24, R4, C16, and C4 interconnects.
Device Routing
All embedded blocks communicate with the logic array similar to
LAB-to-LAB interfaces. Each block (for example, M4K memory,
embedded multiplier, or PLL) connects to row and column interconnects
and has local interconnect regions driven by row and column
interconnects. These blocks also have direct link interconnects for fast
connections to and from a neighboring LAB.
Table 2–1
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shows the Cyclone II device’s routing scheme.
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Destination
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Cyclone II Device Handbook, Volume 1
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Cyclone II Architecture
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2–15
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