EP2C5F256C8 Altera, EP2C5F256C8 Datasheet - Page 48

IC CYCLONE II FPGA 5K 256-FBGA

EP2C5F256C8

Manufacturer Part Number
EP2C5F256C8
Description
IC CYCLONE II FPGA 5K 256-FBGA
Manufacturer
Altera
Series
Cyclone® IIr
Datasheet

Specifications of EP2C5F256C8

Number Of Logic Elements/cells
4608
Number Of Labs/clbs
288
Total Ram Bits
119808
Number Of I /o
158
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
256-FBGA
Family Name
Cyclone® II
Number Of Logic Blocks/elements
4608
# I/os (max)
158
Frequency (max)
402.58MHz
Process Technology
90nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
4608
Ram Bits
119808
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
256
Package Type
FBGA
No. Of Macrocells
4608
Family Type
Cyclone II
No. Of I/o's
158
Clock Management
PLL
I/o Supply Voltage
3.6V
Operating Frequency Max
320MHz
Rohs Compliant
No
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-1446

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0
Embedded Multipliers
Figure 2–19. Embedded Multiplier LAB Row Interface
2–36
Cyclone II Device Handbook, Volume 1
Interconect Region
LAB Block
C4 Interconnects
LAB
Embedded Multiplier
to LAB Row Interface
Block Interconnect Region
Direct Link Interconnect
from Adjacent LAB
16
Embedded Multiplier Routing Interface
The R4, C4, and direct link interconnects from adjacent LABs drive the
embedded multiplier row interface interconnect. The embedded
multipliers can communicate with LABs on either the left or right side
through these row resources or with LAB columns on either the right or
left with the column resources. Up to 16 direct link input connections to
the embedded multiplier are possible from the left adjacent LABs and
another 16 possible from the right adjacent LAB. Embedded multiplier
outputs can also connect to left and right LABs through 18 direct link
interconnects each.
array interface.
Row Interface
36
5
Block
36 Inputs per Row
Figure 2–19
R4 Interconnects
18
16
18
Control
[35..0]
Embedded Multiplier
shows the embedded multiplier to logic
36 Outputs per Row
[35..0]
18 Direct Link Outputs
to Adjacent LABs
36
C4 Interconnects
18
18
Altera Corporation
Interconect Region
Direct Link Interconnect
from Adjacent LAB
LAB Block
February 2007
LAB

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