EP2C20F484C8 Altera, EP2C20F484C8 Datasheet - Page 15
![IC CYCLONE II FPGA 20K 484-FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP2C20F484C8
Manufacturer Part Number
EP2C20F484C8
Description
IC CYCLONE II FPGA 20K 484-FBGA
Manufacturer
Altera
Series
Cyclone® IIr
Datasheet
1.EP2C5T144C8N.pdf
(168 pages)
Specifications of EP2C20F484C8
Number Of Logic Elements/cells
18752
Number Of Labs/clbs
1172
Total Ram Bits
239616
Number Of I /o
315
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Cyclone® II
Number Of Logic Blocks/elements
18752
# I/os (max)
315
Frequency (max)
402.58MHz
Process Technology
90nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
18752
Ram Bits
239616
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
484
Package Type
FBGA
For Use With
P0528 - BOARD DEV DE1 ALTERA544-1736 - CYCLONE II STARTER KIT EP2C20N
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-1365
EP2C20F484C8
EP2C20F484C8
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2C20F484C8
Manufacturer:
FAIRCHILD
Quantity:
9
Company:
Part Number:
EP2C20F484C8
Manufacturer:
ALTERA99
Quantity:
118
Company:
Part Number:
EP2C20F484C8N
Manufacturer:
ALTERA
Quantity:
853
Part Number:
EP2C20F484C8N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Figure 2–2. Cyclone II LE
Altera Corporation
February 2007
(DEV_CLRn)
labclkena1
labclkena2
Chip-Wide
labclk1
labclk2
labclr1
labclr2
Reset
data1
data2
data3
data4
Asynchronous
Clock Enable
Clear Logic
Clock &
Select
LAB Carry-In
Look-Up
Figure 2–2
Each LE’s programmable register can be configured for D, T, JK, or SR
operation. Each register has data, clock, clock enable, and clear inputs.
Signals that use the global clock network, general-purpose I/O pins, or
any internal logic can drive the register’s clock and clear control signals.
Either general-purpose I/O pins or internal logic can drive the clock
enable. For combinational functions, the LUT output bypasses the
register and drives directly to the LE outputs.
Each LE has three outputs that drive the local, row, and column routing
resources. The LUT or register output can drive these three outputs
independently. Two LE outputs drive column or row and direct link
routing connections and one drives local interconnect resources, allowing
the LUT to drive one output while the register drives another output. This
feature, register packing, improves device utilization because the device
can use the register and the LUT for unrelated functions. When using
register packing, the LAB-wide synchronous load control signal is not
available. See
Table
(LUT)
Chain
Carry
shows a Cyclone II LE.
Register Chain
Routing From
Previous LE
“LAB Control Signals” on page 2–8
LAB Carry-Out
Synchronous
LAB-Wide
Synchronous
Load
Clear Logic
Load and
Synchronous
LAB-Wide
Clear
Cyclone II Device Handbook, Volume 1
Register Bypass
Packed
Register Select
D
ENA
CLRN
Register
Feedback
Q
for more information.
Cyclone II Architecture
Programmable
Register
Row, Column,
And Direct Link
Routing
Row, Column,
And Direct Link
Routing
Local Routing
Register Chain
Output
2–3