EP2C20F484C8 Altera, EP2C20F484C8 Datasheet - Page 70
![IC CYCLONE II FPGA 20K 484-FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP2C20F484C8
Manufacturer Part Number
EP2C20F484C8
Description
IC CYCLONE II FPGA 20K 484-FBGA
Manufacturer
Altera
Series
Cyclone® IIr
Datasheet
1.EP2C5T144C8N.pdf
(168 pages)
Specifications of EP2C20F484C8
Number Of Logic Elements/cells
18752
Number Of Labs/clbs
1172
Total Ram Bits
239616
Number Of I /o
315
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Cyclone® II
Number Of Logic Blocks/elements
18752
# I/os (max)
315
Frequency (max)
402.58MHz
Process Technology
90nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
18752
Ram Bits
239616
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
484
Package Type
FBGA
For Use With
P0528 - BOARD DEV DE1 ALTERA544-1736 - CYCLONE II STARTER KIT EP2C20N
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-1365
EP2C20F484C8
EP2C20F484C8
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2C20F484C8
Manufacturer:
FAIRCHILD
Quantity:
9
Company:
Part Number:
EP2C20F484C8
Manufacturer:
ALTERA99
Quantity:
118
Company:
Part Number:
EP2C20F484C8N
Manufacturer:
ALTERA
Quantity:
853
Part Number:
EP2C20F484C8N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
I/O Structure & Features
Figure 2–28. EP2C5 & EP2C8 I/O Banks
Notes to
(1)
(2)
(3)
(4)
(5)
2–58
Cyclone II Device Handbook, Volume 1
3.3-V PCI & PCI-X
Also Supports the
I/O Standards
This is a top view of the silicon die.
This is a graphic representation only. Refer to the pin list and the Quartus II software for exact pin locations.
The LVPECL I/O standard is only supported on clock input pins. This I/O standard is not supported on output
pins.
The differential SSTL-18 and SSTL-2 I/O standards are only supported on clock input pins and PLL output clock
pins.
The differential 1.8-V and 1.5-V HSTL I/O standards are only supported on clock input pins and PLL output clock
pins.
I/O Bank 1
Figure
I/O Bank 1
2–28:
All I/O Banks Support
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
Notes
3.3-V LVTTL/LVCMOS
2.5-V LVTTL/LVCMOS
1.8-V LVTTL/LVCMOS
1.5-V LVCMOS
LVDS
RSDS
mini-LVDS
LVPECL (3)
SSTL-2 Class I and II
SSTL-18 Class I
HSTL-18 Class I
HSTL-15 Class I
Differential SSTL-2 (4)
Differential SSTL-18 (4)
Differential HSTL-18 (5)
Differential HSTL-15 (5)
I/O Bank 2
I/O Bank 4
(1),
(2)
HSTL-18 Class II, & HSTL-15
HSTL-18 Class II, & HSTL-15
I/O Bank 2 Also Supports
I/O Bank 4 Also Supports
Class II I/O Standards
Class II I/O Standards
the SSTL-18 Class II,
the SSTL-18 Class II,
Power Bus
Individual
I/O Bank 3
Altera Corporation
I/O Bank 3
Also Supports the
3.3-V PCI & PCI-X
I/O Standards
February 2007