EP2C20F484C8 Altera, EP2C20F484C8 Datasheet - Page 43
![IC CYCLONE II FPGA 20K 484-FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP2C20F484C8
Manufacturer Part Number
EP2C20F484C8
Description
IC CYCLONE II FPGA 20K 484-FBGA
Manufacturer
Altera
Series
Cyclone® IIr
Datasheet
1.EP2C5T144C8N.pdf
(168 pages)
Specifications of EP2C20F484C8
Number Of Logic Elements/cells
18752
Number Of Labs/clbs
1172
Total Ram Bits
239616
Number Of I /o
315
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Cyclone® II
Number Of Logic Blocks/elements
18752
# I/os (max)
315
Frequency (max)
402.58MHz
Process Technology
90nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
18752
Ram Bits
239616
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
484
Package Type
FBGA
For Use With
P0528 - BOARD DEV DE1 ALTERA544-1736 - CYCLONE II STARTER KIT EP2C20N
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-1365
EP2C20F484C8
EP2C20F484C8
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2C20F484C8
Manufacturer:
FAIRCHILD
Quantity:
9
Company:
Part Number:
EP2C20F484C8
Manufacturer:
ALTERA99
Quantity:
118
Company:
Part Number:
EP2C20F484C8N
Manufacturer:
ALTERA
Quantity:
853
Part Number:
EP2C20F484C8N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Altera Corporation
February 2007
Clock Modes
Table 2–8
memory.
Table 2–9
when configured in the different memory modes.
M4K Routing Interface
The R4, C4, and direct link interconnects from adjacent LABs drive the
M4K block local interconnect. The M4K blocks can communicate with
LABs on either the left or right side through these row resources or with
LAB columns on either the right or left with the column resources. Up to
16 direct link input connections to the M4K block are possible from the
left adjacent LAB and another 16 possible from the right adjacent LAB.
M4K block outputs can also connect to left and right LABs through each
16 direct link interconnects.
array interface.
Independent
Input/output
Read/write
Single
Independent
Input/output
Read/write
Single clock
Table 2–8. M4K Clock Modes
Clock Mode
Table 2–9. Cyclone II M4K Memory Clock Modes
Clocking Modes
summarizes the different clock modes supported by the M4K
shows which clock modes are supported by all M4K blocks
In this mode, a separate clock is available for each port (ports A
and B). Clock A controls all registers on the port A side, while
clock B controls all registers on the port B side.
On each of the two ports, A or B, one clock controls all registers
for inputs into the memory block: data input, wren, and address.
The other clock controls the block’s data output registers.
Up to two clocks are available in this mode. The write clock
controls the block’s data inputs, wraddress, and wren. The
read clock controls the data output, rdaddress, and rden.
control all registers of the memory block. Asynchronous clear
signals for the registers are not supported.
In this mode, a single clock, together with clock enable, is used to
True Dual-Port
Mode
v
v
v
Figure 2–17
Cyclone II Device Handbook, Volume 1
Simple Dual-Port
Description
shows the M4K block to logic
Mode
v
v
v
Cyclone II Architecture
Single-Port Mode
v
v
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