XC5VLX30-1FFG676C Xilinx Inc, XC5VLX30-1FFG676C Datasheet - Page 140
![IC FPGA VIRTEX-5 30K 676FBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VLX30-1FFG676C
Manufacturer Part Number
XC5VLX30-1FFG676C
Description
IC FPGA VIRTEX-5 30K 676FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX30-1FFG676C
Total Ram Bits
1179648
Number Of Logic Elements/cells
30720
Number Of Labs/clbs
2400
Number Of I /o
400
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
676-BBGA, FCBGA
No. Of Logic Blocks
4800
No. Of Gates
30000
Family Type
Virtex-5 LX
No. Of Speed Grades
1
No. Of I/o's
400
Clock Management
PLL
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
122-1559
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Chapter 4: Block RAM
140
Synchronous FIFO
Data flow control is automatic; the user need not be concerned about the block RAM
addressing sequence, although WRCOUNT and RDCOUNT are also brought out, if
needed for special applications.
The user must, however, observe the FULL and EMPTY flags, and stop writing when
FULL is High, and stop reading when EMPTY is High. If these rules are violated, an active
WREN while FULL is High will activate the WRERR flag, and an active RDEN while
EMPTY is High will activate the RDERR flag. In either violation, the FIFO content will,
however, be preserved, and the address counters will stay valid.
Programmable ALMOSTFULL and ALMOSTEMPTY flags are brought out to give the user
an early warning when the FIFO is approaching its limits. Both these flag values can be set
by configuration to (almost) anywhere in the FIFO address range.
Two operating modes affect the reading of the first word after the FIFO is emptied:
•
•
•
Use the EN_SYN = FALSE setting in the following cases:
•
•
•
Virtex-4 FPGA designs used the same FIFO logic for multirate and synchronous FIFOs,
thus flag latency in synchronous FIFOs can vary. By setting the EN_SYN attribute to TRUE
when using Virtex-5 FPGA synchronous FIFOs, any clock cycle latency when asserting or
deasserting flags is eliminated.
First-word fall-through (FWFT) mode is only supported in the multirate FIFO
(EN_SYN = FALSE).
In standard mode, the first word written into an empty FIFO will appear at DO after
the user has activated RDEN. The user must pull the data out of the FIFO.
In FWFT mode, the first word written into an empty FIFO will automatically appear
at DO without the user activating RDEN. The next RDEN will then pull the
subsequent data word onto DO.
Standard and FWFT mode differ only in the reading of the first word entry after the
FIFO is empty.
when the clocks are asynchronous
when the frequencies of the two clocks are the same but the phase is different
when one frequency is a multiple of the other.
Table 4-13
www.xilinx.com
shows the FIFO capacity in the two modes.
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
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