XC5VLX30-1FFG676C Xilinx Inc, XC5VLX30-1FFG676C Datasheet - Page 148
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XC5VLX30-1FFG676C
Manufacturer Part Number
XC5VLX30-1FFG676C
Description
IC FPGA VIRTEX-5 30K 676FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX30-1FFG676C
Total Ram Bits
1179648
Number Of Logic Elements/cells
30720
Number Of Labs/clbs
2400
Number Of I /o
400
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
676-BBGA, FCBGA
No. Of Logic Blocks
4800
No. Of Gates
30000
Family Type
Virtex-5 LX
No. Of Speed Grades
1
No. Of I/o's
400
Clock Management
PLL
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
122-1559
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Chapter 4: Block RAM
148
FIFO Almost Full/Empty Flag Offset Range
The offset ranges for Almost Empty and Almost Full are listed in
Table 4-18: FIFO Data Depth
Table 4-19: FIFO Almost Full/Empty Flag Offset Range
The Almost Full and Almost Empty offsets are usually set to a small value of less than 10
to provide a warning that the FIFO is about to reach its limits. Since the full capacity of any
FIFO is normally not critical, most applications use the ALMOST_FULL flag not only as a
warning but also as a signal to stop writing.
Notes:
1. ALMOST_EMPTY_OFFSET and ALMOST_FULL_OFFSET for any design must be less than the total
Notes:
1. For limitations under certain conditions, refer to
Multirate (Asynchronous) – EN_SYN=FALSE
Synchronous mode – EN_SYN=TRUE
FIFO18
FIFO depth.
FIFO18
x18
x36
x18
x36
x4
x9
x4
x9
x18
x36
Data Width
x4
x9
Data Width
FIFO36
x18
x36
x72
x18
x36
x72
x4
x9
x4
x9
FIFO36
x18
x36
x72
x4
x9
Min
www.xilinx.com
5
5
5
5
5
1
1
1
1
1
Standard
ALMOST_EMPTY_OFFSET
Block RAM
Memory
8192
4096
2048
1024
Max
8187
4091
2043
1019
8190
4094
2046
1022
512
507
510
Equation 4-1
Min
6
6
6
6
6
FWFT
Standard
(1)
8193
4097
2049
1025
513
8188
4092
2044
1020
Max
on
508
page
FIFO Capacity
146.
ALMOST_FULL_OFFSET
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Table
Min
4
4
4
4
4
1
1
1
1
1
4-19.
FWFT
8194
4098
2050
1026
514
Max
8187
4091
2043
1019
8190
4094
2046
1022
507
510
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