XC5VLX30-1FFG676C Xilinx Inc, XC5VLX30-1FFG676C Datasheet - Page 359
XC5VLX30-1FFG676C
Manufacturer Part Number
XC5VLX30-1FFG676C
Description
IC FPGA VIRTEX-5 30K 676FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX30-1FFG676C
Total Ram Bits
1179648
Number Of Logic Elements/cells
30720
Number Of Labs/clbs
2400
Number Of I /o
400
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
676-BBGA, FCBGA
No. Of Logic Blocks
4800
No. Of Gates
30000
Family Type
Virtex-5 LX
No. Of Speed Grades
1
No. Of I/o's
400
Clock Management
PLL
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
122-1559
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Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
DATA_WIDTH Attribute
INTERFACE_TYPE Attribute
The DATA_WIDTH attribute defines the parallel data output width of the serial-to-parallel
converter. The possible values for this attribute depend on the INTERFACE_TYPE and
DATA_RATE attributes. See
Table 8-3: Recommended Data Widths
When the DATA_WIDTH is set to widths larger than six, a pair of ISERDES_NODELAY
must be configured into a master-slave configuration. See
Width expansion is not allowed in memory mode.
The INTERFACE_TYPE attribute determines whether the ISERDES_NODELAY is
configured in memory or networking mode. The allowed values for this attribute are
MEMORY or NETWORKING. The default mode is MEMORY.
When INTERFACE_TYPE is set to NETWORKING, the Bitslip submodule is available and
the OCLK port is unused. BITSLIP_ENABLE must be set to TRUE, and the Bitslip port tied
Low to disable Bitslip operation when the Bitslip module is not used in networking mode.
When set to MEMORY, the Bitslip submodule is not available (BITSLIP_ENABLE must be
set to FALSE), and the OCLK port can be used.
Figure 8-5
mode.
INTERFACE_TYPE
NETWORKING
MEMORY
illustrates the ISERDES_NODELAY internal connections when in Memory
www.xilinx.com
Table 8-3
Input Serial-to-Parallel Logic Resources (ISERDES)
for recommended data widths.
DATA_RATE
DDR
DDR
SDR
SDR
ISERDES Width
Recommended Data Widths
2, 3, 4, 5, 6, 7, 8
4, 6, 8, 10
None
4
Expansion.
359
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