XC5VLX30-1FFG676C Xilinx Inc, XC5VLX30-1FFG676C Datasheet - Page 217
XC5VLX30-1FFG676C
Manufacturer Part Number
XC5VLX30-1FFG676C
Description
IC FPGA VIRTEX-5 30K 676FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX30-1FFG676C
Total Ram Bits
1179648
Number Of Logic Elements/cells
30720
Number Of Labs/clbs
2400
Number Of I /o
400
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
676-BBGA, FCBGA
No. Of Logic Blocks
4800
No. Of Gates
30000
Family Type
Virtex-5 LX
No. Of Speed Grades
1
No. Of I/o's
400
Clock Management
PLL
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
122-1559
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SelectIO Resources
I/O Tile Overview
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Input/output characteristics and logic resources are covered in three consecutive chapters.
Chapter 6, SelectIO Resources
input receivers, and gives detailed examples of many standard interfaces.
SelectIO Logic
Data-Rate (DDR) operation, and the programmable input delay (IDELAY).
Advanced SelectIO Logic
An I/O tile contains two IOBs, two ILOGICs, two OLOGICs, and two IODELAYs.
Figure 6-1
X-Ref Target - Figure 6-1
shows a Virtex-5 FPGA I/O tile.
Resources, describes the input and output data registers and their Double-
(Chapter 7)
(Chapter 7)
(Chapter 8)
(Chapter 7)
(Chapter 8)
(Chapter 7)
(Chapter 8)
(Chapter 7)
(Chapter 8)
(Chapter 7)
OSERDES
OSERDES
www.xilinx.com
Resources, describes the data serializer/deserializer (SERDES).
ISERDES
ISERDES
IODELAY
IODELAY
OLOGIC
OLOGIC
Figure 6-1: Virtex-5 FPGA I/O Tile
ILOGIC
ILOGIC
or
or
or
or
describes the electrical behavior of the output drivers and
(Chapter 6)
(Chapter 6)
IOB
IOB
ug190_6_01_041106
Pad
Pad
Chapter 6
Chapter 7,
Chapter 8,
217
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