XC2V3000-5FGG676C Xilinx Inc, XC2V3000-5FGG676C Datasheet - Page 59

• Manufacturer Part Number: XC2V3000-5FGG676C
• Description: IC VIRTEX-II FPGA 3M 676-FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-IIr

Specifications of XC2V3000-5FGG676C

• Number Of Labs/clbs: 3584
• Total Ram Bits: 1769472
• Number Of I /o: 484
• Number Of Gates: 3000000
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 676-BBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Logic Elements/cells: -
• Other names: 122-1355

IOB Input Switching Characteristics Standard Adjustments
Table 15
Table 15: IOB Input Switching Characteristics Standard Adjustments
DS031-3 (v3.5) November 5, 2007
Product Specification
LVTTL (Low-Voltage Transistor-Transistor Logic)
LVCMOS (Low-Voltage CMOS ), 3.3V
LVCMOS, 2.5V
LVCMOS, 1.8V
LVCMOS, 1.5V
LVDS (Low-Voltage Differential Signaling), 2.5V
LVDS, 3.3V
LVDSEXT (Extended Mode), 2.5V
LVDSEXT, 3.3V
ULVDS (Ultra LVDS), 2.5V
BLVDS (Bus LVDS), 2.5V
LDT (HyperTransport), 2.5V
LVPECL (Low-Voltage Positive Electron-Coupled Logic), 3.3V
PCI (Peripheral Component Interface), 33 MHz, 3.3V
PCI, 66 MHz, 3.3V
PCI-X, 133 MHz, 3.3V
GTL (Gunning Transceiver Logic)
GTL Plus
HSTL (High-Speed Transceiver Logic), Class I
HSTL, Class II
HSTL, Class III
HSTL, Class IV
HSTL, Class I, 1.8V
HSTL, Class II, 1.8V
HSTL, Class III, 1.8V
HSTL, Class IV, 1.8V
SSTL (Stub Series Terminated Logic), Class I, 1.8V
SSTL, Class II, 1.8V
SSTL, Class I, 2.5V
SSTL, Class II, 2.5V
SSTL, Class I, 3.3V
SSTL, Class II, 3.3V
AGP-2X/AGP (Accelerated Graphics Port)
LVDCI (Low-Voltage Digitally Controlled Impedance), 3.3V
LVDCI, 2.5V
LVDCI, 1.8V
LVDCI, 1.5V
gives all standard-specific data input delay adjustments.
R
Description
www.xilinx.com
IOSTANDARD
Virtex-II Platform FPGAs: DC and Switching Characteristics
LVDSEXT_25
LVDSEXT_33
HSTL_III_18
HSTL_IV_18
LVPECL_33
HSTL_II_18
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
HSTL_I_18
ULVDS_25
BLVDS_25
SSTL18_II
Attribute
SSTL18_I
SSTL3_ II
LVDCI_33
LVDCI_25
LVDCI_18
LVDCI_15
LVDS_25
LVDS_33
SSTL2_II
HSTL_IV
PCI33_3
PCI66_3
HSTL_III
SSTL2_I
SSTL3_I
HSTL_II
LDT_25
HSTL_I
LVTTL
GTLP
PCIX
AGP
GTL
T
T
Parameter
T
T
T
T
T
T
T
T
T
T
T
T
ILVDSEXT_25
ILVDSEXT_33
T
T
T
T
T
T
T
IHSTL_IV_18
T
T
T
IHSTL_III_18
ILVPECL_33
T
T
T
IHSTL_II_18
T
T
ILVCMOS33
ILVCMOS25
ILVCMOS18
ILVCMOS15
T
Timing
T
IHSTL_I_18
IULVDS_25
IBLVDS_25
T
ISSTL18_II
T
ISSTL18_I
ILVDCI_33
ILVDCI_25
ILVDCI_18
ILVDCI_15
ILVDS_25
ILVDS_33
T
IHSTL_IV
ISSTL2_II
ISSTL3_II
IPCI33_3
IPCI66_3
T
IHSTL_III
ISSTL2_I
ISSTL3_I
IHSTL_II
ILDT_25
T
T
IHSTL_I
ILVTTL
IGTLP
IPCIX
IAGP
IGTL
0.00
0.00
0.11
0.42
0.98
0.60
0.60
0.68
0.56
0.48
0.68
0.48
0.60
0.00
0.00
0.00
0.42
0.42
0.42
0.42
0.42
0.42
0.42
0.42
0.42
0.42
0.42
0.42
0.42
0.42
0.35
0.35
0.35
0.00
0.11
0.42
0.98
-6
Speed Grade
0.00
0.00
0.11
0.43
1.00
0.60
0.60
0.69
0.56
0.49
0.69
0.49
0.60
0.00
0.00
0.00
0.42
0.42
0.42
0.42
0.42
0.42
0.42
0.42
0.42
0.42
0.42
0.42
0.42
0.42
0.35
0.35
0.35
0.00
0.11
0.43
1.00
-5
0.00
0.00
0.12
0.49
1.15
0.69
0.69
0.79
0.65
0.56
0.79
0.56
0.69
0.00
0.00
0.00
0.48
0.48
0.48
0.48
0.48
0.48
0.48
0.48
0.48
0.48
0.48
0.48
0.48
0.48
0.40
0.40
0.40
0.00
0.12
0.49
1.14
-4
Module 3 of 4
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
11