EP2S60F484I4N Altera, EP2S60F484I4N Datasheet - Page 170

• Manufacturer Part Number: EP2S60F484I4N
• Description: IC STRATIX II FPGA 60K 484-FBGA
• Manufacturer: Altera
• Series: Stratix® IIr

Specifications of EP2S60F484I4N

• Number Of Logic Elements/cells: 60440
• Number Of Labs/clbs: 3022
• Total Ram Bits: 2544192
• Number Of I /o: 334
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 484-FBGA
• Family Name: Stratix II
• Number Of Logic Blocks/elements: 60440
• # I/os (max): 334
• Frequency (max): 711.24MHz
• Process Technology: 90nm (CMOS)
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 60440
• Ram Bits: 2544192
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• For Use With: 544-1700 - DSP KIT W/STRATIX II EP2S60N544-1697 - NIOS II KIT W/STRATIX II EP2S60N
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-1910; EP2S60F484I4N

Timing Model
5–34
Stratix II Device Handbook, Volume 1
Notes to
(1)
(2)
(3)
(4)
t
t
t
t
t
t
t
t
t
Symbol
S U
H
C O
C L R
P R E
C L K L
C L K H
L U T
A D D E R
Table 5–37. LE_FF Internal Timing Microparameters
These numbers apply to -3 speed grade EP2S15, EP2S30, EP2S60, and EP2S90 devices.
These numbers apply to -3 speed grade EP2S130 and EP2S180 devices.
For the -3 and -5 speed grades, the minimum timing is for the commercial temperature grade. Only -4 speed grade
devices offer the industrial temperature grade.
For the -4 speed grade, the first number is the minimum timing parameter for industrial devices. The second
number is the minimum timing parameter for commercial devices.
Table
LE register setup time before
clock
LE register hold time after clock
LE register clock-to-output
delay
Minimum clear pulse width
Minimum preset pulse width
Minimum clock low time
Minimum clock high time
5–37:
Parameter
Internal Timing Parameters
See
Tables 5–37
Min
149
204
204
612
162
354
612
(3)
90
62
Grade
-3 Speed
through
Max
(1)
378
619
94
5–42
Min
157
214
214
642
642
162
354
(3)
95
62
Grade
-3 Speed
for internal timing parameters.
Max
(2)
397
650
99
Min
104
104
172
172
234
234
234
234
703
703
703
703
162
170
354
372
(4)
59
62
-4 Speed
Grade
Max
109
435
712
Altera Corporation
Min
121
200
273
273
820
820
162
354
(3)
62
-5 Speed
Grade
Max
127
507
829
April 2011
Unit
ps
ps
ps
ps
ps
ps
ps
ps
ps