EP2S60F484I4N Altera, EP2S60F484I4N Datasheet - Page 228
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EP2S60F484I4N
Manufacturer Part Number
EP2S60F484I4N
Description
IC STRATIX II FPGA 60K 484-FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet
1.EP2S15F484I4N.pdf
(238 pages)
Specifications of EP2S60F484I4N
Number Of Logic Elements/cells
60440
Number Of Labs/clbs
3022
Total Ram Bits
2544192
Number Of I /o
334
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
484-FBGA
Family Name
Stratix II
Number Of Logic Blocks/elements
60440
# I/os (max)
334
Frequency (max)
711.24MHz
Process Technology
90nm (CMOS)
Operating Supply Voltage (typ)
1.2V
Logic Cells
60440
Ram Bits
2544192
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
484
Package Type
FC-FBGA
For Use With
544-1700 - DSP KIT W/STRATIX II EP2S60N544-1697 - NIOS II KIT W/STRATIX II EP2S60N
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-1910
EP2S60F484I4N
EP2S60F484I4N
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2S60F484I4N
Manufacturer:
NANYA
Quantity:
30
Company:
Part Number:
EP2S60F484I4N
Manufacturer:
ALTERA
Quantity:
238
Part Number:
EP2S60F484I4N
Manufacturer:
ALTERA
Quantity:
20 000
PLL Timing Specifications
5–92
Stratix II Device Handbook, Volume 1
Notes to
(1)
(2)
t
t
f
f
f
f
% spread
t
t
t
L O C K
D L O C K
S W I T C H OV E R
C L B W
V C O
S S
P L L _ P S E R R
A R E S E T
A R E S E T _ R E C O N F I G
Table 5–92. Enhanced PLL Specifications (Part 2 of 2)
Limited by I/O f
If the counter cascading feature of the PLL is utilized, there is no minimum output clock frequency.
Name
Table
5–92:
M A X
Time required for the
PLL to lock from the
time it is enabled or
the end of device
configuration
Time required for the
PLL to lock
dynamically after
automatic clock
switchover between
two identical clock
frequencies
Frequency range
where the clock
switchover performs
properly
PLL closed-loop
bandwidth
PLL VCO operating
range for –3 and –4
speed grade devices
PLL VCO operating
range for –5 speed
grade devices
Spread-spectrum
modulation frequency
Percent down spread
for a given clock
frequency
Accuracy of PLL
phase shift
Minimum pulse width
on
Minimum pulse width
on the
when using PLL
reconfiguration. Reset
the PLL after
scandone
high.
. See
areset
Description
areset
Table 5–78 on page 5–69
goes
signal.
signal
0.13
Min
300
300
500
0.4
30
10
4
for the maximum. Cannot exceed f
0.03
1.20
Typ
0.5
16.90
1,040
Max
±15
500
840
150
0.6
1
1
O U T
specification.
Altera Corporation
April 2011
MHz
MHz
MHz
MHz
Unit
kHz
ms
ms
ps
ns
ns
%