EP2S60F484I4N Altera, EP2S60F484I4N Datasheet - Page 87
![IC STRATIX II FPGA 60K 484-FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP2S60F484I4N
Manufacturer Part Number
EP2S60F484I4N
Description
IC STRATIX II FPGA 60K 484-FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet
1.EP2S15F484I4N.pdf
(238 pages)
Specifications of EP2S60F484I4N
Number Of Logic Elements/cells
60440
Number Of Labs/clbs
3022
Total Ram Bits
2544192
Number Of I /o
334
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
484-FBGA
Family Name
Stratix II
Number Of Logic Blocks/elements
60440
# I/os (max)
334
Frequency (max)
711.24MHz
Process Technology
90nm (CMOS)
Operating Supply Voltage (typ)
1.2V
Logic Cells
60440
Ram Bits
2544192
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
484
Package Type
FC-FBGA
For Use With
544-1700 - DSP KIT W/STRATIX II EP2S60N544-1697 - NIOS II KIT W/STRATIX II EP2S60N
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-1910
EP2S60F484I4N
EP2S60F484I4N
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2S60F484I4N
Manufacturer:
NANYA
Quantity:
30
Company:
Part Number:
EP2S60F484I4N
Manufacturer:
ALTERA
Quantity:
238
Part Number:
EP2S60F484I4N
Manufacturer:
ALTERA
Quantity:
20 000
Figure 2–53. Input Timing Diagram in DDR Mode
Altera Corporation
May 2007
Input To
Logic Array
Data at
input pin
CLK
B0
When using the IOE for DDR outputs, the two output registers are
configured to clock two data paths from ALMs on rising clock edges.
These output registers are multiplexed by the clock to drive the output
pin at a ×2 rate. One output register clocks the first bit out on the clock
high time, while the other output register clocks the second bit out on the
clock low time.
Figure 2–55
A0
B1
A0
B0
A1
shows the DDR output timing diagram.
Figure 2–54
B2
A1
B1
A2
B3
A2
B2
shows the IOE configured for DDR output.
A3
B4
A3
B3
Stratix II Device Handbook, Volume 1
Stratix II Architecture
2–79