EP2S60F484I4N Altera, EP2S60F484I4N Datasheet - Page 23
![IC STRATIX II FPGA 60K 484-FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP2S60F484I4N
Manufacturer Part Number
EP2S60F484I4N
Description
IC STRATIX II FPGA 60K 484-FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet
1.EP2S15F484I4N.pdf
(238 pages)
Specifications of EP2S60F484I4N
Number Of Logic Elements/cells
60440
Number Of Labs/clbs
3022
Total Ram Bits
2544192
Number Of I /o
334
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
484-FBGA
Family Name
Stratix II
Number Of Logic Blocks/elements
60440
# I/os (max)
334
Frequency (max)
711.24MHz
Process Technology
90nm (CMOS)
Operating Supply Voltage (typ)
1.2V
Logic Cells
60440
Ram Bits
2544192
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
484
Package Type
FC-FBGA
For Use With
544-1700 - DSP KIT W/STRATIX II EP2S60N544-1697 - NIOS II KIT W/STRATIX II EP2S60N
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-1910
EP2S60F484I4N
EP2S60F484I4N
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2S60F484I4N
Manufacturer:
NANYA
Quantity:
30
Company:
Part Number:
EP2S60F484I4N
Manufacturer:
ALTERA
Quantity:
238
Part Number:
EP2S60F484I4N
Manufacturer:
ALTERA
Quantity:
20 000
Altera Corporation
May 2007
Figure 2–11. ALM in Arithmetic Mode
While operating in arithmetic mode, the ALM can support simultaneous
use of the adder's carry output along with combinational logic outputs. In
this operation, the adder output is ignored. This usage of the adder with
the combinational logic output provides resource savings of up to 50% for
functions that can use this ability. An example of such functionality is a
conditional operation, such as the one shown in
equation for this example is:
To implement this function, the adder is used to subtract ‘Y’ from ‘X.’ If
‘X’ is less than ‘Y,’ the carry_out signal is ‘1.’ The carry_out signal is
fed to an adder where it drives out to the LAB local interconnect. It then
feeds to the LAB-wide syncload signal. When asserted, syncload
selects the syncdata input. In this case, the data ‘Y’ drives the
syncdata inputs to the registers. If ‘X’ is greater than or equal to ‘Y,’ the
syncload signal is de-asserted and ‘X’ drives the data port of the
registers.
datae0
datae1
dataf0
dataf1
datab
dataa
datad
datac
R = (X < Y) ? Y : X
4-Input
4-Input
4-Input
4-Input
LUT
LUT
LUT
LUT
carry_out
carry_in
Stratix II Device Handbook, Volume 1
adder0
adder1
D
D
reg0
reg1
Figure
Q
Q
Stratix II Architecture
2–12. The
To general or
To general or
To general or
To general or
local routing
local routing
local routing
local routing
2–15